M263 datasheet(302/398 Pages) NUVOTON

302 / 398 page

M261/M262/M263

Mar 25, 2020

Page 302 of 398

Rev 1.02

6.6

General Purpose I/O (GPIO)

6.6.1

Overview

This chip has up to 107 General Purpose I/O pins to be shared with other function pins depending on

the chip configuration. These 107 pins are arranged in 8 ports named as PA, PB, PC, PD, PE, PF, PG

and PH. PA, PB and PE has 16 pins on port. PC has 14 pins on port. PD has 15 pins on port. PF has

12 pins on port. PG has 10 pins on port. PH has 8 pins on port. Each of the 107 pins is independent

and has the corresponding register bits to control the pin mode function and data.

The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,

Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are

depending on CIOINI (CONFIG0[10]).

6.6.2

Features



Four I/O modes:

–

Quasi-bidirectional mode

–

Push-Pull Output mode

–

Open-Drain Output mode

–

Input only with high impendence mode



TTL/Schmitt trigger input selectable



I/O pin can be configured as interrupt source with edge/level setting



Supports High Drive and High Slew Rate I/O mode



Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting

–

CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset

–

CIOINI = 1, all GPIO pins in input mode after chip reset



I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode



Enabling the pin interrupt function will also enable the wake-up function



Improve access efficiency by using single cycle I/O bus.

M263 Datasheet(PDF) 302 Page - Nuvoton Technology Corporation

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