M263 datasheet(299/398 Pages) NUVOTON

299 / 398 page

M261/M262/M263

Mar 25, 2020

Page 299 of 398

Rev 1.02

and CLK_CLKSEL3 register.

6.3.5

Power-down Mode Clock

When entering Power-down mode, system clocks, some clock sources and some peripheral clocks

are disabled. Some clock sources and peripherals clock are still active in Power-down mode.

For theses clocks, which still keep active, are listed below:



Clock Generator

–

10 kHz internal low speed RC oscillator (LIRC) clock

–

32.768 kHz external low speed crystal oscillator (LXT) clock



Peripherals Clock (When the modules adopt LXT or LIRC as clock source)

6.3.6

Clock Output

This device is equipped with a power-of-2 frequency divider which is composed by 16 chained divide-

by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is

reflected to CLKO function pin. Therefore, there are 16 options of power-of-2 divided clocks with the

frequency from Fin/2

1 to F

in/2

16 where F

in is input clock frequency to the clock divider.

The output formula is Fout = Fin/2

(N+1), where F

in is the input clock frequency, Fout is the clock divider

output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]). When writing 1 to

CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to CLKOEN

(CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state and

stays in low state.

If DIV1EN(CLK_CLKOCTL[5]) set to 1, the clock output clock (CLKO_CLK) will bypass power-of-2

frequency divider. The output divider clock will be output to CLKO pin directly.

When entering Power-down mode, clock output does not out put clock even if the CKO clock source is

LXT.

Note:

Before clock switching, both the pre-selected and newly selected clock sources must be turned on and

stable.

0000

0001

1110

1111

16 to 1

MUX

1/2

…...

FREQSEL

(CLK_CLKOCTL[3:0])

CLKO

16 chained

divide-by-2 counter

CLKOEN

(CLK_CLKOCTL[4])

Enable

divide-by-2 counter

DIV1EN

(CLK_CLKOCTL[5])

CLK1HZEN

(CLK_CLKOCTL[6])

1 Hz clock from RTC

LXT

LIRC

RTCSEL(CLK_CLKSEL3[8])

/32768

HCLK

LXT

HXT

HIRC

CLKOSEL (CLK_CLKSEL1[29:28])

CLKOCKEN

(CLK_APBCLK0[6])

Figure 6.3-8 Clock Output Block Diagram

M263 Datasheet(PDF) 299 Page - Nuvoton Technology Corporation

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