| Electronic Components Datasheet Search |
|
XRT79L71 Datasheet(PDF) 95 Page - Exar Corporation |
|
|
|||||||||||||||||||||||||||||
XRT79L71 Datasheet(HTML) 95 Page - Exar Corporation |
|
95 / 441 page ![]() áç áç áç áç PRELIMINARY XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC REV. P1.0.3 83 OPERATION INTERRUPT ENABLE REGISTER - BYTE 0 (ADDRESS = 0X0117) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Receive UTOPIA/ POS-PHY Interface Block Interrupt Enable Unused Receive ATM Cell/PPP Processor Block Interrupt Enable Transmit UTOPIA/ POS-PHY Interface Block Interrupt Enable Unused Transmit ATM Cell/PPP Processor Block Interrupt Enable R/W R/O R/O R/W R/W R/O R/O R/W 0 0000 000 BIT NUMBER NAME TYPE DESCRIPTION 7 Receive UTOPIA/POS-PHY Interface Block Interrupt Enable R/W Receive UTOPIA/POS-PHY Interface Block Interrupt Enable: This READ/WRITE bit permit the user to either enable or disable the Receive UTOPIA/POS-PHY Interface Block for interrupt gen- eration. If the user writes a "0" to this register bit and disables the "Receive UTOPIA/POS-PHY Interface Block" (for interrupt generation), then all "Receive UTOPIA/POS-PHY Interface Block" interrupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individual "Receive UTOPIA/POS-PHY Interface Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "Receive UTOPIA/POS-PHY Interface Block" interrupts within the device. 1 - Enables the "Receive UTOPIA/POS-PHY Interface Block" at the "Block-Level". 6 - 5 Unused R/O 4 Receive ATM Cell/PPP Processor Block Interrupt Enable R/W Receive ATM Cell/PPP Processor Block Interrupt Enable: This READ/WRITE bit permit the user to either enable or disable the Receive ATM Cell/PPP Processor Block for interrupt genera- tion. If the user writes a "0" to this register bit and disables the "Receive ATM Cell/PPP Processor Block" (for interrupt genera- tion), then all "Receive ATM Cell/PPP Processor Block" inter- rupts will be disabled for interrupt generation. If the user writes a "1" to this register bit, he/she will still need to enable the individ- ual "Receive ATM Cell/PPP Processor Block" interrupt(s) at the "Source Level" in order to enable that particular interrupt. 0 - Disable all "Receive ATM Cell/PPP Processor Block" inter- rupts within the device. 1 - Enables the "Receive ATM Cell/PPP Processor Block" at the "Block-Level". |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |