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W5100 Datasheet(PDF) 40 Page - WIZnet Co., Ltd |
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W5100 Datasheet(HTML) 40 Page - WIZnet Co., Ltd |
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40 / 72 page  © Copyright 2009-2011 WIZnet Co., Inc. All rights reserved. 39 gS2_RX_BASE = gS1_BASE + (gS1_MASK + 1); gS2_RX_MASK = 2K – 1 ; gS3_RX_BASE = gS2_BASE + (gS2_MASK + 1); gS3_RX_MASK = 2K – 1 ; TMSR = 0x55; // assign 2K tx memory per socket. Same method, set gS0_TX_BASE, gS0_TX_MASK, gS1_TX_BASE, gS1_TX_MASK, gS2_TX_BASE, gS2_TX_MASK, gS3_TX_BASE and gS3_TX_MASK. } In case of, assign 4K,2K,1K,1K. { RMSR = 0x06; // assign 4K,2K,1K,1K rx memory per socket. gS0_RX_BASE = chip_base_address + RX_memory_base_address(0x6000); gS0_RX_MASK = 4K – 1 ; // 0x0FFF, for getting offset address within assigned socket 0 RX memory. gS1_RX_BASE = gS0_BASE + (gS0_MASK + 1); gS1_RX_MASK = 2K – 1 ; // 0x07FF gS2_RX_BASE = gS1_BASE + (gS1_MASK + 1); gS2_RX_MASK = 1K – 1 ; // 0x03FF gS3_RX_BASE = gS2_BASE + (gS2_MASK + 1); gS3_RX_MASK = 1K – 1 ; // 0x03FF TMSR = 0x06; // assign 4K,2K,1K,1K rx memory per socket. Same method, set gS0_TX_BASE, gS0_TX_MASK, gS1_TX_BASE, gS1_TX_MASK, gS2_TX_BASE, gS2_TX_MASK, gS3_TX_BASE and gS3_TX_MASK. } |
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