W5100 datasheet(24/72 Pages) WIZNET

24 / 72 page

(S1_IR)”. This bit will be automatically cleared when S1_IR is cleared to

0x00.

S0_INT

Occurrence of Socket 0 Socket Interrupt

It is set in case that interrupt occurs at the socket 0. For more detailed

information of socket interrupt, refer to “Socket 0 Interrupt Register

(S0_IR)”. This bit will be automatically cleared when S0_IR is cleared to

0x00.

IMR (Interrupt Mask Register) [R/W] [0x0016] [0x00]

The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to

a bit in the Interrupt Register (IR). If an interrupt mask bit is set, an interrupt will be issued

whenever the corresponding bit in the IR is set. If any bit in the IMR is set as ‘0’, an interrupt

will not occur though the bit in the IR is set.

IM_IR7

IM_IR6

IM_IR5

Reserved

IM_IR3

IM_IR2

IM_IR1

IM_IR0

Bit

Symbol

Description

IM_IR7

IP Conflict Enable

IM_IR6

Destination unreachable Enable

IM_IR5

PPPoE Close Enable

Reserved

It should be set as ‘0’

IM_IR3

Occurrence of Socket 3 Socket Interrupt Enable

IM_IR2

Occurrence of Socket 2 Socket Interrupt Enable

IM_IR1

Occurrence of Socket 1 Socket Interrupt Enable

IM_IR0

Occurrence of Socket 0 Socket Interrupt Enable

RTR (Retry Time-value Register) [R/W] [0x0017 – 0x0018] [0x07D0]

This register sets the period of timeout. Value 1 means 100us. The initial value is

2000(0x07D0). That will be set as 200ms.

Ex) For 400ms configuration, set as 4000(0x0FA0)

0x0017

0x0018

0x0F

0xA0

Re-transmission will occur if there is no response from the remote peer to the commands of

CONNECT, DISCON, CLOSE, SEND, SEND_MAC and SEND_KEEP, or the response is delayed.

W5100 Datasheet(PDF) 24 Page - WIZnet Co., Ltd

W5100 Datasheet(HTML) 24 Page - WIZnet Co., Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL