MPC5777C datasheet(66/90 Pages) NXP

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3.13.9 DSPI timing with CMOS and LVDS pads

NOTE

The DSPI in TSB mode with LVDS pads can be used to

implement the Micro Second Channel (MSC) bus protocol.

DSPI channel frequency support is shown in Table 42. Timing specifications are shown

in Table 43, Table 44, Table 45, Table 46, and Table 47.

Table 42. DSPI channel frequency support

DSPI use mode

Max usable frequency (MHz)1, 2

CMOS (Master mode)

Full duplex – Classic timing (Table 43)

Full duplex – Modified timing (Table 44)

Output only mode (SCK/SOUT/PCS) (Table 43 and Table 44)

Output only mode TSB mode (SCK/SOUT/PCS) (Table 47)

LVDS (Master mode)

Full duplex – Modified timing (Table 45)

Output only mode TSB mode (SCK/SOUT/PCS) (Table 46)

1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

2. Maximum usable frequency does not take into account external device propagation delay.

3.13.9.1 DSPI master mode full duplex timing with CMOS and LVDS pads

3.13.9.1.1 DSPI CMOS Master Mode — Classic Timing

Table 43. DSPI CMOS master classic timing (full duplex and output only) –

MTFE = 0, CPHA = 0 or 11

Symbol

Characteristic

Condition2

Value3

Unit

Pad drive4

Load (CL)

Min

Max

tSCK

SCK cycle time

PCR[SRC]=11b

25 pF

33.0

—

PCR[SRC]=10b

50 pF

80.0

—

PCR[SRC]=01b

50 pF

200.0

—

tCSC

PCS to SCK delay

PCR[SRC]=11b

25 pF

(N5 × tSYS, 6) – 16

—

PCR[SRC]=10b

50 pF

(N5 × tSYS, 6) – 16

—

PCR[SRC]=01b

50 pF

(N5 × tSYS, 6) – 18

—

PCS: PCR[SRC]=01b

SCK: PCR[SRC]=10b

50 pF

(N5 × tSYS, 6) – 45

—

Table continues on the next page...

Electrical characteristics

MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020.

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