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MPC5777C Datasheet(PDF) 76 Page - NXP Semiconductors |
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MPC5777C Datasheet(HTML) 76 Page - NXP Semiconductors |
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76 / 90 page  3.13.9.1.4 DSPI Master Mode – Output Only Table 46. DSPI LVDS master timing — output only — timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock1, 2 # Symbol Characteristic Condition3 Value4 Unit Pad drive5 Load (CL) Min Max 1 tSCK SCK cycle time LVDS 15 pF to 50 pF differential 25 — ns 2 tCSV PCS valid after SCK6 (SCK with 50 pF differential load cap.) PCR[SRC]=11b 25 pF — 8 ns PCR[SRC]=10b 50 pF — 12 ns 3 tCSH PCS hold after SCK6 (SCK with 50 pF differential load cap.) PCR[SRC]=11b 0 pF –4.0 — ns PCR[SRC]=10b 0 pF –4.0 — ns 4 tSDC SCK duty cycle (SCK with 50 pF differential load cap.) LVDS 15 pF to 50 pF differential 1/2tSCK – 2 1/2tSCK + 2 ns SOUT data valid time (after SCK edge) 5 tSUO SOUT data valid time from SCK7 LVDS 15 pF to 50 pF differential — 6 ns SOUT data hold time (after SCK edge) 6 tHO SOUT data hold time after SCK7 LVDS 15 pF to 50 pF differential –7.0 — ns 1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may degrade for weaker output drivers. 2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1. 3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified otherwise. 4. All timing values for output signals in this table are measured to 50% of the output voltage. 5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation. 6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This timing value is due to pad delays and signal propagation delays. 7. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. Table 47. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or 1, continuous SCK clock 1, 2 # Symbol Characteristic Condition3 Value4 Unit Pad drive5 Load (CL) Min Max 1 tSCK SCK cycle time PCR[SRC]=11b 25 pF 33.0 — ns PCR[SRC]=10b 50 pF 80.0 — ns PCR[SRC]=01b 50 pF 200.0 — ns 2 tCSV PCS valid after SCK6 PCR[SRC]=11b 25 pF 7 — ns PCR[SRC]=10b 50 pF 8 — ns PCR[SRC]=01b 50 pF 18 — ns PCS: PCR[SRC]=01b SCK: PCR[SRC]=10b 50 pF 45 — ns Table continues on the next page... Electrical characteristics MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 14, 01/2020. 76 NXP Semiconductors |
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