Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

Freescale Semiconductor

3

SIU16

Bus Busy Disable Mode Can Hang 60X Bus in Multi-Master Systems

Date Added: 5/21/2002

Description: The bus busy disable mode (SIUMCR[BBD=1]) can not be used if the MSC8101

is not the only master on the 60X bus. Using this mode in such a system can cause the 60X bus to

hang.

Workaround:

1.

If the external master supports the ABB signal, do not use the bus busy disable

mode and connect this signal to the MSC8101. The DBB signal can either be con-

nected or can be pulled up.

2.

If the external master does not support the ABB signal do one of the following:

a. Do not use the bus busy disable mode and generate the ABB signal

externally. The DBB signal can either be connected or can be pulled up.

The following external ABB implementation should be sufficient to work

around the problem: Assert the ABB signal whenever a qualified bus

grant for the external master is sampled (Bus grant asserted while

ARTRY and ABB are negated). Negate the ABB signal when there is no

qualified bus grant. The negation of ABB should be as follows: Drive

ABB to VDD for half a clock cycle and then stop driving it (HIGH-Z).

b. If using the internal arbiter and up to two external masters, connect the

external bus grants (through an AND gate if more than one) to an

available external bus request and define the priority for that request to

be the highest in the PPC_ALRH register. The DBB signal can either be

connected or can be pulled up.

Fix Plan: TBD

0K40A

SIU18

ARTRY Assertion When Using Pipeline Depth of Zero

Date Added: 10/15/2002

Description: Internal (60x) slave maintains a pipeline depth of zero by asserting AACK only af-

ter TA. When ARTRY is asserted the 60x bus access will be terminated and TA will not be as-

serted. Therefore the Internal (60x) slave will not assert AACK since TA was not asserted.

Workaround: Use a pipeline depth of one (BCR[PLDP]=0) for applications that require memory

coherency.

Fix Plan: TBD

0K40A

SIU19

Bus Monitor Timeout When Using External Slave

Date Added: 10/15/2002

Description: When using an external 60x bus slave with the bus monitor activated, PSDVAL is

not asserted when the external slave is accessed, which could cause the bus monitor to time-out

and TEA to be asserted.

Workaround: The following workarounds

1.

Use pipeline depth of zero (BCR[PLDP]=1) when using an external 60x bus slave.

2.

Disable 60X bus monitor, SYPCR[PBME]=0.

3.

If the external 60x bus slave is another 810x or 826x device, connect the PSDVAL

signals together.

Fix Plan: TDB

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask