Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

Freescale Semiconductor

9

SC5

SC140 CORE May Hang After Illegal Execution Set

Date Added: 2/19/2002

Description: Upon receipt of an illegal execution set the SC140 CORE may enter a freeze state

that can only be released by reset.

Workaround: No workaround available.

System Number: 7541

Fix Plan: TBD

0K40A

SC6

Incorrect Data on Trace Buffer Read During Core Freeze

Date Added: 2/19/2002

Description: After writing data to the Trace Buffer, the TB is disabled, in order to read from it.

There are 2 options to read the TB and the problem occurs in both:

1.

Reading the TB by software.

If, While reading the TB by SW into a core register, there is a core freeze, One data over-

write the previous data.

2.

Reading the TB from the JTAG.

If the JTAG reads the TB while there is a core freeze, the data will not be correctly

sampled.

Workaround:

1.

Software:

Read the TB by software, when there is no core freeze:

a. The program will be in internal memory.

b. Make sure the EFCOP is not working.

c. Make sure the local bus to L1 memory is not working.

d. The Write-Buffer is empty.

e. There are no other move commands except for the TB read.

2.

JTAG:

a. Read the TB from JTAG only when the core is in DEBUG mode.

b. Before reading the TB, flush the Write-Buffer.

System Number: 7604

Fix Plan: TBD

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask