Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

2

Freescale Semiconductor

SIU4

Incorrect Masking of MCP

Date Added: 5/30/2000:

Description: MCP (Machine Check Interrupt) due to data errors (parity / ECC) is masked by the

SWRI bit in SYPCR.

Workaround: Clear the SWRI bit in SYPCR to get data errors indication.

System Number: 3695

Fix Plan: Rev A

0K40A

SIU8

Parity Checking Error

Date Added: 6/13/2000:

Description: During a read from a device with port size less than 64 bits, from an address not

aligned to 64 bits, the parity bits for parity check are not taken from the correct locations. For ex-

ample, for a read of 4 bytes from a 32-bit port size from address 4, the parity is checked against

DP[4–7] while it should be checked against DP[0–3]. The bug exists for both normal and rmw

parity, and for both PowerPC and Local buses.

Workaround: None

System Number: 5839

Fix Plan: RevA

0K40A

SIU9

Bus Monitor Asserts Spurious TEA After Address Retry.

Date Added: 1/28/2001

Description: The bus monitor will not recognize the competition of an Address Retry transaction

and will assert TEA if there is no bus activity for a time equal to the expiration time.

Workaround: Disable the bus monitor in systems where Address Retry cycles are used (e.g. sys-

tems which include PowerSpan).

Fix Plan: Rev A

0K40A

SIU10

Strict Enforcement of Requirement to Assert DBG and TS in Same Cycle When Core En-

abled

Date Added: 1/28/2001

Description: This is a compatibility note. An external arbiter must assert DBG in the same clock

in which TS is asserted (there may be a one clock delay if the PPC_ACR[DBGD] bit is set, how-

ever, after reset this bit is not set by default). Some external arbiters, including the one implement-

ed in PowerSpan, violate this requirement. As a result, the system hangs following the first bus

access after reset.

Workaround: Use only a compliant external arbiter or the internal MSC8101 arbiter.

Fix Plan: Rev A

0K40A

SIU13

SDAMUX not Valid in Single-MSC8101 Mode

Date Added: 3/14/2002

Description: SDAMUX signal is disabled (stuck at’0’)when SDRAM machine handles the

memory access and the chip is programmed to single-MSC8101 mode (BCR[EBM]=0).

Workaround: None.

Fix Plan: TBD

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask