Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

6

Freescale Semiconductor

QSIU16

ALE Output During Reset

Date Added: 2/20/2003

Description: ALE behavior is not guaranteed during reset. This affects only multi-master sys-

tems which perform reset configuration from external memory and which use ALE for all memory

accesses. ALE recovers with the first access after reset.

Workaround: None

System Number:

Fix Plan: RevA

0K40A

DMA1

DMA Data Corruption on either PPC Bus or Local Bus

Date Added: 2/19/2002

Description: Data transferred by the DMA on either the PPC Bus or Local Bus may be corrupted.

Workaround: For DMA accesses on the PPC Bus - disable PPC bus pipeline by setting

BCR[PLDP]=1. For DMA accesses on the Local Bus the UPMC programming patch is available.

System Number: 7462

Fix Plan: RevA

0K40A

EFC1

Inaccurate EFCOP IIR Outputs For Two or Fewer Coefficients

Date Added: 2/19/2002

Description: When using normal (dual) DMA or fly-by DMA transfers which have maximum

transfer size greater than 32-bits with the EFCOP to perform IIR filtering with two or less IIR co-

efficients, the first output of IIR filter will be lost. The rest of the outputs will be shifted and inac-

curate.

Use only DMA 32-bit maximum transfer size for both input and output channels.

Fix Plan: Not currently scheduled.

0K40A

BOOT1

Incorrect Checksum for Host Bootload

Date Added: 8/15/2000:

Description: The host bootload calculates erroneous checksum.

Workaround: Clear ICR[HF3] so that the host bootload ignores the checksum comparison re-

sult.

System Number: 6178

Fix Plan: Rev A

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask