Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

8

Freescale Semiconductor

GEN1

Device Withstands MM ESD of 75V Instead of 100V

Date Added: 5/21/2002

Description: Device meets the ESD specifications for Human Body Model (HBM) of 1000V and

Charged Device Model (CDM) of 500V but does not withstand the Machine Model (MM) re-

quirement of 100V. All pins guaranteed to withstand 75V MM.

Workaround: None.

Fix Plan: RevA

0K40A

GEN2

Unexpected Outputs During Boundary Scan

Date Added: 10/18/2002

Description: D[32:60] outputs may behave indeterminately during boundary scan.

Workaround: Reset the device by asserting PORESET while HPE/EE1=0. Alternatively, assert

PORESET throughout boundary scan.

Fix Plan: RevA

0K40A

SC1

PC Cannot Be Updated in Debug Mode Entered From Asynchronous Interrupt

Date Added: 10/5/2000

Description: When a DEBUG instruction is executed in a static or dynamic delay slot created by

an asynchronous interrupt, the core enters Debug mode, but the PC cannot be updated.

Workaround: In the dynamic case, the debugger can use a status bit in the ESR, which indicates

whether the core entered a debug in a delay slot. Software workarounds are available for all the

static cases. A detailed description was sent by StarCore and can be resent upon request.

Fix Plan: RevA

0K40A

SC3

Erroneous Trace Buffer Value

Date Added: 10/5/2000

Description: An erroneous 62-bit value may be written to the trace buffer when the EOnCE is

programmed to write both event counters (ECNT_VAL and ECNT_EXT).

Workaround: None.

Fix Plan: RevA

0K40A

SC4

SC140 May Hang After Write To PCTL0 Register.

Date Added: 2/19/2002

Description: Write to PCTL0 immediately freezes the core for 150-900 cycles. If the system is

busy (e.g. pre-fetch transactions), the core may not exit the freeze state.

Workaround:

Option A:

1.

Make sure the EFCOP is not working.

2.

Make sure the local bus to L1 memory is not working.

3.

The program that writes to PCTL0 is in internal memory.

4.

Write to PCTL0 immediately after reset before any external data accesses.

Option B: Do not write to PCTL0.

System Number: 7560

Fix Plan: TBD

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask