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MSC8101 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MSC8101 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 28 page ![]() Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5 10 Freescale Semiconductor SC7 Change of Flow May Cause Incorrect Trace-Buffer Data Date Added: 2/19/2002 Description: When programing the EOnCE for tracing events of change of flow (TCHOF) and interrupts (TINT), the Trace-Buffer will be updated on every event by the source and destination addresses. In the event of a CHOF (change of flow) to another CHOF with an interrupt request in between, the Trace-Buffer will be updated with additional data. The additional data is incorrect and is not needed for the trace. Workaround: Perform post-processing after reading the Trace-Buffer. Search in the data for a source address and the destination before it should be the destination of that source. That means there is a destination which came before its source. Delete the source and the previous data. 7794 Fix Plan: TBD 0K40A SC8 Debug Exception Request Form JTAG is Not Accepted During Core Freeze Date Added: 5/21/2002 Description: JTAG debug exception request is not accepted by the Core during freeze. If the re- quest is asserted and negated during core freeze, the request will be discarded. Workaround: Assert Debug request from JTAG. When entering the exception routine, assert by software an external pin (EE pin for example), to signal the exception Service Routine is now ex- ecuted. After that, a new JTAG instruction can be written. Fix Plan: TBD 0K40A SC9 EE Pins Do Not Enable Different EOnCE Modules During Core Freeze Date Added: 5/21/2002 Description: If EE pins are asserted to enable events in EOnCE during core freeze and the request is negated during the same core freeze, the event is not enabled. Workaround: Poll on Core status from JTAG. Assert the EE pin(s) until the Core is not in freeze for at least 3 cycles. Fix Plan: TBD 0K40A CPM2 CAM Access Not Atomic Date Added: 5/30/2000: Description: The bus atomicity mechanism for CAM access may not function correctly when the CPM’s DMA accesses the CAM. This only affects systems in which multiple CPMs will ac- cess the CAM. Workaround: None System Number: 1410 Fix Plan: Rev A 0K40A CPM4 No CTS Lost Indication with HDLC Date Added: 5/30/2000 Description: When CTS is negated at the end of an HDLC frame, (last flag or one bit before) transmission will be aborted. However, there is no CTS-LOST indication. There is only an abort indication. Workaround: None System Number: 1670 Fix Plan: Rev A 0K40A Table 2. Silicon Errata (Continued) Errata Number Errata Description Applies to Mask |
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