Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

Freescale Semiconductor

7

BOOT2

Boot Interference in Multi-Master System with Shared Memory

Date Added: 8/5/2001

Description: The DSPRAM address in the memory map as programmed by the boot loader code

in the ROM is the same for all processors. During simultaneous boot, this will cause interference

of one processor with another.

Workaround: For up to 4 MSC8101’s including the configuration master.

Boot the processors one after the other, and not at the same time. Reprogram unique

DSPRAM address for each processor. The configuration master is set also to be the

arbitration master and the memory controller for the system. The configuration word for

the master should set the MMR field of the reset word (bits [18:19]) to 2’b11. This will

mask all the external bus requests of the configuration slaves. After the master completes

its boot, the user should:

1.

Clear all external requestors from the Arbitration Level Register (ALR) of the arbi-

tration master.

2.

Reprogram the UPM of the DSPRAM bank to unique address (see programming

example below)

3.

Set priority for the next configuration slave in the Arbitration Level Register

(ALR) of the arbitration master.

4.

Enable external bus requests by clearing SIUMCR MMR field (bits [16:17]).

5.

Repeat stages 2,3 for consecutive slaves.

Configuration master programming code:

move.l PPC_ALRH,D7 ; Step #1

move.l PPC_ALRL,D8

bmclr.w #$f,D7.L

bmclr.w #$ff00,D8.H

move.l D7,PPC_ALRH

move.l D8,PPC_ALRL

upmc_init $04000000 ; Step #2 (DSPRAM base address

$0400_0000)

move.l PPC_ALRH,D7 ; Step #3

nop

bmset.w #$7,D7.L

nop

move.l D7,PPC_ALRH

move.l SIUMCR,D7; Step #4

nop

bmclr.w #$c000,D7.L

nop

move.l D7,SIUMCR

Fix Plan: RevA

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask