LTC3370 datasheet(18/26 Pages) AD

18 / 26 page

LTC3307A

Rev. A

For more information www.analog.com

Low EMI PCB Layout

The LTC3307A is specifically designed to minimize

EMI/EMC emissions and also to maximize efficiency

and improve transient response when switching at

high frequencies.

See Figure 3 for a recommended PCB layout.

For optimal performance the LTC3307A requires that

both input supply VIN pins (Pins 3, 8) each have a local

decoupling capacitor with their ground terminals soldered

directly to the ground plane on the top layer near PGND

pins (Pins 4, 7). These capacitors provide the AC current

to the internal power MOSFETs and their drivers. Large,

switched currents flow in the VIN and PGND pins and the

input capacitors. The loops formed by the input capacitors

should be as small as possible by placing the capacitors

adjacent to the VIN and PGND pins. Capacitors with small

case size such as 0603 are optimal due to lowest parasitic

Figure 3a.

3307A F03

PGND

AGND

VOUT

COUT1

COUT2

CIN1

CFF

CIN2

CIN4

CIN3

PGND

VIN

GROUND PLANE ON LAYER 2

CBYP

Recommended PCB Layout for the LTC3307A

Small Solution Size

inductance. Even smaller 0201 capacitors can additionally

be placed right next to the respective VIN and PGND pins

for better performance with minimal (if at all) increase in

application footprint. In addition, place a local, unbroken

ground plane under the application circuit on the layer

closest to the surface layer.

Decoupling AGND is also very important. Place a small

analog bypass 0201 or 0402 capacitor as close as pos-

sible to the LTC3307A directly on the traces leading from

VIN (Pin 3) and AGND (Pin 1).

Place the inductor on the same side of the circuit board.

The trace connecting SW pins (Pins 5, 6) to the inductor

should be as short as possible to reduce radiated EMI and

parasitic coupling.

Keep the FB and RT nodes small and far away or shielded

from the noisy SW node.

APPLICATIONS INFORMATION

3307A F03b

PGND

AGND

COUT3

COUT1

COUT4

COUT2

VOUT

CIN1

CFF

CIN2

CIN4

CIN3

PGND

VIN

GROUND PLANE ON LAYER 2

CBYP

Figure 3b. Recommended PCB Layout for the LTC3307A with

capacitors COUT1 and COUT2 rotated by 90°, which reduces high-

frequency output ripple. Optional 0201 capacitors COUT3 and

COUT4 further improve the high-frequency output ripple

LTC3370 Datasheet(PDF) 18 Page - Analog Devices

LTC3370 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL