LTC6906 datasheet(15/34 Pages) AD

15 / 34 page

LTC6992-1/LTC6992-2/

LTC6992-3/LTC6992-4

Rev. D

For more information www.analog.com

OPERATION

The LTC6992 is built around a master oscillator with a

1MHz maximum frequency. The oscillator is controlled

by the SET pin current (ISET) and voltage (VSET), with a

1MHz • 50k conversion factor that is accurate to ±0.8%

under typical conditions.

fMASTER =

tMASTER

= 1MHz • 50k •

ISET

VSET

A feedback loop maintains VSET at 1V ±30mV, leaving ISET

as the primary means of controlling the output frequency.

The simplest way to generate ISET is to connect a resistor

(RSET) between SET and GND, such that ISET = VSET/RSET.

The master oscillator equation reduces to:

fMASTER =

tMASTER

1MHz • 50k

RSET

From this equation, it is clear that VSET drift will not affect

the output frequency when using a single program resis-

tor (RSET). Error sources are limited to RSET tolerance and

the inherent frequency accuracy ∆fOUT of the LTC6992.

RSET may range from 50k to 800k (equivalent to ISET

between 1.25μA and 20μA).

The LTC6992 includes a programmable frequency divider

which can further divide the frequency by 1, 4, 16, 64,

256, 1024, 4096 or 16384 before driving the OUT pin.

The divider ratio NDIV is set by a resistor divider attached

to the DIV pin.

fOUT =

tOUT

1MHz • 50k

NDIV

•

ISET

VSET

With RSET in place of VSET/ISET the equation reduces to:

fOUT =

tOUT

1MHz • 50k

NDIV •RSET

DIVCODE

The DIV pin connects to an internal, V+ referenced 4-bit

A/D converter that determines the DIVCODE value.

DIVCODE programs two settings on the LTC6992:

1. DIVCODE determines the output frequency divider set-

ting, NDIV.

2. DIVCODE determines the output polarity, via the POL

bit.

VDIV may be generated by a resistor divider between V+

and GND as shown in Figure 2.

Figure 1. Simple Technique for Setting DIVCODE

6992 F01

LTC6992

V+

DIV

GND

2.25V TO 5.5V

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