Matched Broadband RF VGA

400MHz to 2700MHz

Glitch-Free

22

Rev 3, April 2015

IDTF0480NBGI

Datasheet

Pin

Name

Function

1, 5, 6, 7, 24,

25, 26, 27, 28,

29, 30, 31, 32

N.C.

No Connection. Not internally connected. OK to connect to VCC. OK to

connect to GND.

2, 4, 14, 16, 18,

21, 23

GND

Ground these pins.

3

RFIN

RF input internally matched to 50

. Must use external DC block as close

to the pin as possible.

8

SPI Data

1

Data input: 3.3V or 1.8V CMOS compatible. Set LogicCTL pin 11 for

desired logic voltage.

9

SPI CLK

1

Clock input: 3.3V or 1.8V CMOS compatible. Set LogicCTL pin 11 for

desired logic voltage.

10

SPI CSb

1

Chip Select input: 3.3V or 1.8V CMOS compatible. Set LogicCTL pin 11 for

desired logic voltage. Active LOW shifts data.

11

LogicCTL

pull-up resistor connects between the input and Vcc/2. For 1.8V logic,

connect 0 Ω resistor to GND.

12

VCC

5 V Power Supply. Tie to VCC and connect 2 bypass capacitors with

values 1000 pf (closest to pin) and 0.1 µF. See Typical Application Circuit

for details.

13

VCC

5 V Power Supply. Tie to VCC and connect 2 bypass capacitors with

values 1000 pf (closest to pin) and 0.1 µF. See Typical Application Circuit

for details.

15

Band_Select

Leave pin open circuited for lowband select and connect 0 Ω resistor to

GND for highband select. A ~1.5Mohm pull-up resistor connects between

the input and VCC. 3.3V and 1.8V CMOS logic compatible.

17

STBY

Standby (Low/Open = device power ON, High = device power OFF with

SPI still powered ON). A ~1Mohm pull-down resistor connects between

the input and GND. 3.3V and 1.8V CMOS logic compatible

19

R_Bias1

Connect external resistor to GND to optimize amplifier bias. Used in

conjunction with pin 20.

20

R_Bias2

Connect external resistor to GND to optimize amplifier bias. Used in

conjunction with pin 19.

22

RFOUT

RF output. Must use external DC block as close to the pin as possible.

33

— EP

Exposed Pad. Internally connected to GND. Solder this exposed pad to a

PCB pad that uses multiple ground vias to provide heat transfer out of

the device into the PCB ground planes. These multiple via grounds are

also required to achieve the noted RF performance.

1. The SPI interface should be built up by an 8-bit word where 5 bits are used for attenuation setting (see

F0480 DVGA Attenuation word truth table above).