AT90PWM2 datasheet(111/365 Pages) ATMEL

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AT90PWM2/3

4317B–AVR–02/05

how waveforms are generated on the Output Compare outputs OCnx. For more details

about advanced counting sequences and waveform generation, see “16-bit

Timer/Counter1 with PWM” on page 104.

The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation

selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events

and give them a time-stamp indicating time of occurrence. The external signal indicating

an event, or multiple events, can be applied via the ICPn pin or alternatively, via the

analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-

cycle, and other features of the signal applied. Alternatively the time-stamps can be

used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 44. The ele-

ments of the block diagram that are not directly a part of the Input Capture unit are gray

shaded. The small “n” in register and bit names indicates the Timer/Counter number.

Figure 44. Input Capture Unit Block Diagram

When a change of the logic level (an event) occurs on the Input Capture pin (ICPn),

alternatively on the Analog Comparator output (ACO), and this change confirms to the

setting of the edge detector, a capture will be triggered. When a capture is triggered, the

16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The

Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied

into ICRn Register. If enabled (ICIEn = 1), the Input Capture Flag generates an Input

Capture interrupt. The ICFn Flag is automatically cleared when the interrupt is executed.

Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O

bit location.

Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the

low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high

byte is copied into the high byte temporary register (TEMP). When the CPU reads the

ICRnH I/O location it will access the TEMP Register.

ICFn (Int.Req.)

WRITE

ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPnB

Edge

Detector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICPSEL1

ICNC

ICES

AT90PWM2 Datasheet(PDF) 111 Page - ATMEL Corporation

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