AT90PWM2 datasheet(118/365 Pages) ATMEL

118 / 365 page

118

AT90PWM2/3

4317B–AVR–02/05

Figure 48. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In

addition the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set

when either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts

are enabled, the interrupt handler routine can be used for updating the TOP and com-

pare values.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the Compare Registers. If the TOP value is lower

than any of the Compare Registers, a compare match will never occur between the

TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are

masked to zero when any of the OCRnx Registers are written.

The procedure for updating ICRn differs from updating OCRnA when used for defining

the TOP value. The ICRn Register is not double buffered. This means that if ICRn is

changed to a low value when the counter is running with none or a low prescaler value,

there is a risk that the new ICRn value written is lower than the current value of TCNTn.

The result will then be that the counter will miss the compare match at the TOP value.

The counter will then have to count to the MAX value (0xFFFF) and wrap around start-

ing at 0x0000 before the compare match can occur. The OCRnA Register however, is

double buffered. This feature allows the OCRnA I/O location to be written anytime.

When the OCRnA I/O location is written the value written will be put into the OCRnA

Buffer Register. The OCRnA Compare Register will then be updated with the value in

the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is

done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By

using ICRn, the OCRnA Register is free to be used for generating a PWM output on

OCnA. However, if the base PWM frequency is actively changed (by changing the TOP

value), using the OCRnA as TOP is clearly a better choice due to its double buffer

feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the

OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an

inverted PWM output can be generated by setting the COMnx1:0 to three (see Table on

page 125). The actual OCnx value will only be visible on the port pin if the data direction

for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by set-

ting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn,

TCNTn

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

AT90PWM2 Datasheet(PDF) 118 Page - ATMEL Corporation

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