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AT90PWM2 Datasheet(PDF) 225 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 225 Page - ATMEL Corporation |
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225 / 365 page ![]() 225 AT90PWM2/3 4317B–AVR–02/05 Each time bit in the Manchester serial frame is divided into two phases (See Figure 109). The counter counts during the first phase and counts down during the second one. When the data bit transition is detected, the counter memorises the N1 counter value and start counting down. When the counter reachs the zero value, it starts counting up again and the N1/2 value allows to open the next detection window. This detection window defines the time zone where the next data bit edge is sampled. Figure 109. Manchester Decoder operation Start Bit Bit 1 Bit 2 N1 N2 N3 N1/2 N2/2 N3/2 N2/2 Data Clock Manchester Data Manchester Decoder Counter Detection Window Internal Manchester Clock Decoded Data- |
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