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AT90PWM2 Datasheet(PDF) 270 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 270 Page - ATMEL Corporation |
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270 / 365 page  270 AT90PWM2/3 4317B–AVR–02/05 Digital to Analog Converter input Register – DACH and DACL DACH and DACL registers contain the value to be converted into analog voltage. Writing the DACL register forbid the update of the input value until DACH has not been written too. So the normal way to write a 10-bit value in the DAC register is firstly to write DACL the DACH. In order to work easily with only 8 bits, there is the possibility to left adjust the input value. Like this it is sufficient to write DACH to update the DAC value. DALA = 0 DALA = 1 To work with the 10-bit DAC, two registers have to be updated. In order to avoid inter- mediate value, the DAC input values which are really converted into analog signal are buffering into unreachable registers. In normal mode, the update of the shadow register is done when the register DACH is written. In case DAATE bit is set, the DAC input values will be updated on the trigger event selected through DATS bits. In order to avoid wrong DAC input values, the update can only be done after having writ- ten respectively DACL and DACH registers. It is possible to work on 8-bit configuration by only writing the DACH value. In this case, update is done each trigger event. In case DAATE bit is cleared, the DAC is in an automatic update mode. Writing the DACH register automatically update the DAC input values with the DACH and DACL register values. It means that whatever is the configuration of the DAATE bit, changing the DACL regis- ter has no effect on the DAC output until the DACH register has also been updated. So, to work with 10 bits, DACL must be written first before DACH. To work with 8-bit config- uration, writing DACH allows the update of the DAC. Bit 7 65 43 21 0 - - ---- DAC9 DAC8 DACH DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 DACL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 00 00 Bit 7 65 43 21 0 DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DACH DAC1 DAC0 - - - - - - DACL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 00 00 |
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