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AT90PWM2 Datasheet(PDF) 313 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 313 Page - ATMEL Corporation |
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313 / 365 page ![]() 313 AT90PWM2/3 4317B–AVR–02/05 SPI Timing Characteristics See Figure 149 and Figure 150 for details. Figure 149. SPI Interface Timing Requirements (Master Mode) Table 134. SPI Timing Parameters Description Mode Min. Typ. Max. 1 SCK period Master See Table 73 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master TBD 4 Setup Master TBD 5HoldMaster TBD 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master TBD 8 SCK to out high Master TBD 9 SS low to out Slave TBD 10 SCK period Slave 4 • tck 11 SCK high/low Slave 2 • tck 12 Rise/Fall time Slave TBD 13 Setup Slave TBD 14 Hold Slave TBD 15 SCK to out Slave TBD 16 SCK to SS high Slave TBD 17 SS high to tri-state Slave TBD 18 SS low to SCK Slave TBD MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 |
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