LTC4449 datasheet(30/48 Pages) AD

30 / 48 page

LTC7872

Rev. 0

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Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VLOW shifts by an

amount equal to ∆ILOAD • ESR, where ESR is the effective

series resistance of COUT at VLOW. ∆ILOAD also begins to

charge or discharge COUT generating the feedback error sig-

nal that forces the regulator to adapt to the current change

and return VLOW to its steady-state value. During this recov-

ery time VLOW can be monitored for excessive overshoot

or ringing, which would indicate a stability problem. The

availability of the ITH pin not only allows optimization of

control loop behavior but also provides a DC-coupled and

AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining the

rise time at the pin. The ITH external components shown in

the Typical Application circuit will provide an adequate start-

ing point for most applications. The ITH series RC-CC filter

sets the dominant pole-zero loop compensation. The values

can be modified slightly (from 0.5 to 2 times their suggested

values) to optimize transient response once the final PC

layout is done and the particular output capacitor type and

value have been determined. The output capacitors need to

be selected because the various types and values determine

the loop gain and phase. An output current pulse of 20% to

80% of full-load current having a rise time of 1μs to 10μs

will produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET directly across

the output capacitor and driving the gate with an appropri-

ate signal generator is a practical way to produce a realistic

load step condition. The initial output voltage step resulting

from the step change in output current may not be within

the bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better to

look at the ITH pin signal which is in the feedback loop and

is the filtered and compensated control loop response. The

gain of the loop will be increased by increasing RC and the

out of the driver supply that is typically much larger

than the control circuit current. In continuous mode,

IGATECHG = f(QT + QB), where QT and QB are the gate

charges of the top and bottom MOSFETs.

3. I2R losses are predicted from the DC resistances of

the fuse (if used), MOSFETs, inductor and current

sense resistor. In continuous mode, the average output

current flows through L and RSENSE, but is chopped

between the top MOSFET and the bottom MOSFET.

If the two MOSFETs have approximately the same

RDS(ON), then the resistance of one MOSFET can sim-

ply be summed with the resistances of L and RSENSE to

obtain I2R losses. For example, if each RDS(ON) = 10mΩ,

RL = 10mΩ, RSENSE = 5mΩ, then the total resistance

is 25mΩ. This results in losses ranging from 0.6% to

3% as the output current increases from 3A to 15A for

a 12V output in buck mode.

Efficiency varies as the inverse square of VLOW for the

same external components and output power level. The

combined effects of increasingly lower output voltages

and higher currents required by high performance digi-

tal systems is not doubling but quadrupling the impor-

tance of loss terms in the switching regulator system!

4. Transition losses apply only to the top MOSFET(s), and

become significant only when operating at high VHIGH

voltages (typically 15V or greater). Transition losses

can be estimated from:

Transition Loss = (1.7) VHIGH2 • IO(MAX) • CRSS • f

IO(MAX) = Maximum Load on VLOW

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

losses can be minimized by making sure that CHIGH has

adequate charge storage and very low ESR at the switch-

ing frequency. Other losses including Schottky conduc-

tion losses during dead time and inductor core losses

generally account for less than 2% total additional loss.

APPLICATIONS INFORMATION

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