LTC4449 datasheet(33/48 Pages) AD

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LTC7872

Rev. 0

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3. Update the 8-bit PEC as PEC[7] = PEC[6],

PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2,

PEC[1] = IN1, PEC[0] = IN0.

4. Go back to step 2 until all data are shifted. The 8-bit

result is the final PEC byte.

An example to calculate the PEC is listed in Table 6 and

Figure 14. The PEC of the 1 byte data 0x01 is computed

as 0xC7 after the last bit of the byte clocked in.

For the serial port write sequence, the master calculates

the PEC byte for the address byte and data byte it sends

out. The master latches the PEC byte it calculates at the

15th clock falling edge and attaches the calculated PEC

byte following the data byte it shifts out. The LTC7872

also calculates PEC byte for the address byte and data

byte it receives. The LTC7872 latches the PEC byte it cal-

culates at the 16th clock rising edge and compares it with

the PEC byte following the data byte. The data is regarded

as valid only if the PEC bytes match.

For the serial port read sequence, the LTC7872 calculates

PEC byte for the received address byte and data byte it

sends out. The LTC7872 latches the PEC byte at the 15th

clock falling edge and attaches the calculated PEC byte

following the data byte it shifts out. The master calculates

PEC byte for the address byte it sends and data byte it

receives. The master latches the PEC byte at the 16th

clock rising edge and compares it with the PEC byte fol-

lowing the data byte it receivers. The data is regarded as

valid only if the PEC bytes match.

serial bus master on SDI contains the destination register

address (ADDR0) and a following 0 indicating a write.

The next byte is the DATA0 intended for the register at

address ADDR0. The third byte is the PEC0. CSB is then

taken high to terminate the transfer. The first byte of the

second burst contains the destination register address

(ADDR1) and a following 0 indicating a write. The next

byte on SDI is the DATA1 intended for the register at

address ADDR1. The third byte is the PEC1. CSB is then

taken high to terminate the transfer. Note that the written

data is transferred to the internal register at the falling

edge of the 24th clock cycle (parallel load) in each burst

after the PEC is checked as valid.

PEC Byte

The PEC byte a cyclic redundancy check (CRC) value cal-

culated for all the bits in a register group in the order they

are passed, using the initial PEC value of 01000001 (0x41)

and the following characteristic polynomial:

x8 + x2 + x + 1

To calculate the 8-bit PEC value, a simple procedure can

be established:

1. Initialize the PEC to 0100 0001.

2. For each bit DIN coming into the register group, set

IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0,

IN2 = PEC[1] XOR IN0.

APPLICATIONS INFORMATION

Table 6. Procedure to Calculate PEC Byte

CLOCK

CYCLE

DIN

IN0

IN1

IN2

PEC[7]

PEC[6]

PEC[5]

PEC[4]

PEC[3]

PEC[2]

PEC[1]

PEC[0]

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