LTC4449 datasheet(29/48 Pages) AD

29 / 48 page

LTC7872

Rev. 0

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If the duty cycle falls below what can be accommodated by

the minimum on-time, the controller will begin to skip cycles.

The output voltage and current will continue to be regulated,

but the voltage ripple and current ripple will increase. The

minimum on-time for the LTC7872 is approximately 150ns,

with good PCB layout, minimum 30% inductor current rip-

ple and at least 2mV ripple on the current sense signal or

equivalent 10mV between SNSA+ and SNS– pins.

The minimum on-time can be affected by PCB switch-

ing noise in the voltage and current loop. As the peak

sense voltage decreases, the minimum on-time gradu-

ally increases. This is of particular concern in forced

continuous applications with low ripple current at light

loads. If the duty cycle drops below the minimum on-

time limit in this situation, a significant amount of cycle

skipping can occur with correspondingly larger current

and voltage ripple.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

the losses in LTC7872 circuits: 1) IC VHIGH current, 2)

MOSFET driver current, 3) I2R losses, 4) top MOSFET

transition losses.

1. The VHIGH current is the DC supply current given in the

Electrical Characteristics table. VHIGH current typically

results in a small (<0.1%) loss.

2. The MOSFET driver current results from switching the

gate capacitance of the power MOSFETs. Each time

a MOSFET gate is switched from low to high to low

again, a packet of charge dQ moves from the driver

supply to ground. The resulting dQ/dt is a current

The ILIM, SETCUR, FREQ, MODE, BUCK, and DRVSET

pins may or may not be tied together based on conve-

nience. When tying these pins together, please be aware

of the pull-up/down currents/resistors on these pins! Any

external resistor or resistor divider network must take

those into account. For example, each FREQ pin sources

20μA. When two LTC7872 ICs have their FREQ pins tied

together, that is 40μA.

The OVLOW, OVHIGH and UVHIGH pins of multiple LTC7872s

must be tied together. This enables the entire system to

react to an OV/UV condition appropriately. The resistor

divider used on these pins must be scaled based on the

number of LTC7872s paralleled, as these pins have 5μA

hysteresis currents that turn on and off.

The ITHLOW and ITHHIGH pins of multiple LTC7872s

should be tied together. Tying the ITHLOW pins together

and the ITHHIGH pins together gives the best current shar-

ing between phases. Each error amplifier’s compensation

network must be placed local to the specific IC to mini-

mize jitter and stability issues.

The RUN pins must be tied together – this is very critical

for boost mode operation. In boost mode, when multiple

LTC7872 have their RUN pins connected together, care

must be taken to ensure that the logic signal on the RUN

pin is a clean fast rising/falling signal so all ICs are enabled

at the same instant. If a resistor divider is used on the

RUN pin, then the part must be started up in buck mode.

Using a resistor divider on the RUN pin off VHIGH, set for

a start-up voltage higher than the UVHIGH set point, allows

the part to soft start cleanly after a UVHIGH fault is cleared.

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time duration

that the LTC7872 is capable of turning on the top MOSFET.

It is determined by internal timing delays, power stage

timing delays and the gate charge required to turn on the

top MOSFET. Low duty cycle applications may approach

this minimum on-time limit and care should be taken to

ensure that:

tON(MIN) <

VLOW

VHIGH f()

APPLICATIONS INFORMATION

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