LTC4449 datasheet(43/48 Pages) AD

43 / 48 page

LTC7872

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 15.

RHIGH

VHIGH

VLOW

CHIGH

CLOW

SW2

SW1

RSENSE

RLOW

7872 F15

BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH

Branch Current Waveforms (Buck Mode Shown)

6. Keep the switching nodes away from sensitive small-

signal nodes (SNSD+, SNSA+, SNS–, VFB). Ideally the

switch nodes printed circuit traces should be routed

away and separated from the IC and especially the

quiet side of the IC. Separate the high dV/dt traces

from sensitive small-signal nodes with ground traces

or ground planes.

7. Use a low impedance source such as a logic gate to

drive the SYNC pin and keep the PCB trace as short

as possible.

8. The ceramic capacitors between each ITH pin and sig-

nal ground should be placed as close as possible to

the IC. Figure 15 illustrates all branch currents in a

switching regulator. It becomes very clear after study-

ing the current waveforms why it is critical to keep

the high switching current paths to a small physical

size. High electric and magnetic fields will radiate from

these loops just as radio stations transmit signals. The

CLOW ground should return to the negative terminal of

CHIGH and not share a common ground path with any

switched current paths. The left half of the circuit gives

rise to the noise generated by a switching regulator.

The ground terminations of the bottom MOSFET and

Schottky diode should return to the bottom plate(s) of

the VHIGH capacitor(s) with a short isolated PC trace

since very high switched currents are present. External

OPTI-LOOP® compensation allows overcompensation

for PC layouts which are not optimized, but this is not

the recommended design procedure.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 15. Check the following in the

PC layout:

1. The DRVCC bypass capacitor should be placed imme-

diately adjacent to the IC between the DRVCC pin and

the GND plane. A 1μF ceramic capacitor of the X7R or

X5R type is small enough to fit very close to the IC. An

additional 4.7μF to 10μF of ceramic, tantalum or other

very low ESR capacitance is recommended in order to

keep the internal IC supply quiet.

2. The V5 bypass capacitor should be placed immediately

adjacent to the IC between the V5 and the SGND pins.

A 4.7μF to 10μF capacitor of ceramic, tantalum or other

very low ESR capacitance is recommended.

3. Place the feedback divider between the + and – terminals

of CLOW/CHIGH. Route VFBLOW/VFBHIGH with minimum

PC trace spacing from the IC to the feedback dividers.

4. Are the SNSA+, SNSD+ and SNS– printed circuit traces

routed together with minimum PC trace spacing? The

filter capacitors between SNSA+, SNSD+ and SNS–

should be as close as possible to the pins of the IC.

5. Do the (+) plates of CHIGH decoupling cap connect to

the drain of the topside MOSFET as closely as pos-

sible? This capacitor provides the pulsed current to

the MOSFET.

LTC4449 Datasheet(PDF) 43 Page - Analog Devices

LTC4449 Datasheet(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL