LTC4449 datasheet(31/48 Pages) AD

31 / 48 page

LTC7872

Rev. 0

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Communication Sequence

The serial bus is comprised of CSB, SCLK, SDI and SDO.

Data transfers to the part are accomplished by the serial

bus master device first taking CSB low to enable the

LTC7872’s port. Input data applied on SDI is clocked on

the rising edge of SCLK, with all transfers MSB first. The

communication burst is terminated by the serial bus mas-

ter returning CSB high. See Figure 9 for details.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC7872 connected in parallel on the serial bus), as SDO

is high impedance (Hi-Z) when CSB = 1, or when data is

not being read from the part. If the LTC7872 is not used

in a multidrop configuration, or if the serial port mas-

ter is not capable of setting the SDO line level between

read sequences, it is recommended to attach a resistor

between SDO and V5 to ensure the line returns to V5 dur-

ing Hi-Z states. The resistor value should be large enough

to ensure that the SDO output current does not exceed

10mA. See Figure 10 for details.

bandwidth of the loop will be increased by decreasing CC.

If RC is increased by the same factor that CC is decreased,

the zero frequency will be kept the same, thereby keeping

the phase shift the same in the most critical frequency range

of the feedback loop. The output voltage settling behavior

is related to the stability of the closed-loop system and will

demonstrate the actual overall supply performance. A sec-

ond, more severe transient is caused by switching in loads

with large (>1μF) supply bypass capacitors. The discharged

bypass capacitors are effectively put in parallel with CLOW,

causing a rapid drop in VLOW. No regulator can alter its

delivery of current quickly enough to prevent this sudden

step change in output voltage if the load switch resistance

is low and it is driven quickly. If the ratio of CLOAD to COUT is

greater than 1:50, the switch rise time should be controlled

so that the load rise time is limited to approximately 25 •

CLOAD. Thus a 10μF capacitor would require a 250μs rise

time, limiting the charging current to about 200mA.

SERIAL PORT

The SPI-compatible serial port provides control and moni-

toring functionality.

APPLICATIONS INFORMATION

Figure 9.

MASTER–CSB

MASTER–SCLK

tCSS

tCS

tCH

DATA

7872 F09

tCKL

tCKH

tCSS

tCSH

MASTER–SDI

Serial Port Write Timing Diagram

Figure 10.

MASTER–CSB

MASTER–SCLK

LTC7872–SDO

7872 F10

8TH CLOCK

DATA

tDO

Serial Port Read Timing Diagram

LTC4449 Datasheet(PDF) 31 Page - Analog Devices

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