PCI1031PDV datasheet(39/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 13. PCI Command Register

BIT

TYPE

FUNCTION

15–10

Reserved. Bits 15–10 are read only and return 0s when read.

Fast back-to-back enable. Bit 9 indicates whether the device is enabled for the fast back-to-back transaction function. The

PCI1031 does not support fast back-to-back PCI cycles. Bit 9 is read only and returns 0s when read.

R/W

System error (SERR) enable. Bit 8 and bit 6 must be set for the PCI1031 to report address parity errors.

0 = Disable the SERR output driver (default)

1 = Enable the SERR output driver

Wait cycle control. Bit 7 indicates whether a PCI device is capable of address/data stepping. The PCI1031 does not

support address/data stepping; therefore, bit 7 is hardwired to 0. Bit 7 is read only and returns 0s when read. Writes to

bit 7 have no effect.

R/W

Parity error response. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by

asserting SERR.

0 = PCI1031 ignores detected parity error (default)

1 = PCI1031 responds to detected parity errors

VGA palette snoop. Bit 5 controls how PCI devices handle accesses to VGA palette registers. The PCI1031 does not

support VGA palette snooping; therefore, bit 5 is hardwired to 0. Bit 5 is read only and returns 0s when read. Writes to

bit 5 have no effect.

Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and invalidate

commands. The PCI1031 controller uses memory-write commands instead of memory-write- and-invalidate commands;

therefore, bit 4 is hardwired to 0. Bit 4 is read only and returns 0s when read. Writes to bit 4 have no effect.

Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1031 does not monitor

special cycle operations; therefore, bit 3 is hardwired to 0. Bit 3 is read only and returns 0s when read. Writes to bit 3 have

no effect.

R/W

Bus initiator control. Bit 2 controls whether or not a PCI device can act as a PCI bus initiator. Bit 2 is used for distributed

DMA only.

0 = Disables the PCI1031’s ability to generate PCI bus accesses (default)

1 = Enables the PCI1031’s ability to generate PCI bus accesses

R/W

Memory space control. Bit 1 controls whether or not a PCI device can claim cycles in PCI memory space.

0 = Disables the PCI1031’s response to memory space accesses (default)

1 = Enables the PCI1031’s response to memory space accesses

R/W

I/O space control. Bit 0 controls whether or not a PCI device can claim cycles in PCI I/O space.

0 = Disables the PCI1031’s response to I/O space accesses (default)

1 = Enables the PCI1031’s response to I/O space accesses

PCI status register

Bit

Name

PCI status

Type

R/W

Default

PCI status

Type:

Read only, read/write (see individual bit descriptions)

Offset:

06h

Default:

0200h

Description: The PCI status register provides PCI -related device information to the host system. Bits in this

reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. Refer to

Table 14 for a complete description of the register contents.

PCI1031PDV Datasheet(PDF) 39 Page - Texas Instruments

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