PCI1031PDV datasheet(65/100 Pages) TI

65 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ExCA I/O window control register (index 07h)

Bit

Name

ExCA I/O window control

Type

R/W

Default

ExCA

I/O window control

Type:

Read/write (see individual bit descriptions)

Offset:

CardBus socket address + 807h; Card A ExCA offset 07h

Card B ExCA offset 47h

Default:

00h

Description: The ExCA I/O window control register contains parameters related to I/O window sizing and

cycle timing. Refer to Table 31 for a complete description of the register contents.

Table 31. ExCA

I/O Window Control Register (Index 07h)

BIT

TYPE

FUNCTION

R/W

I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit

accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. Bit 7 is encoded as:

0 = 16-bit cycles have standard length (default).

1 = 16-bit cycles are extended by one equivalent ISA wait state.

R/W

I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit

accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. Bit 6 is encoded as:

0 = 8-bit cycles have standard length (default).

1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

R/W

I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses the IOIS16 signal

from the PC Card to determine the data width of the I/O data transfer. Bit 5 is encoded as:

0 = Window data width is determined by I/O window 1 data sizing bit, bit 4 (default).

1 = Window data width is determined by IOIS16.

R/W

I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if the I/O window 1 IOIS16 source bit

(bit 5) is set. Bit 4 is encoded as:

0 = Window data width is 8 bits (default).

1 = Window data width is 16 bits.

R/W

I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit

accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. Bit 3 is encoded as:

0 = 16-bit cycles have standard length (default).

1 = 16-bit cycles are extended by one equivalent ISA wait state.

R/W

I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit

accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. Bit 2 is encoded as:

0 = 8-bit cycles have standard length (default).

1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

R/W

I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data-sizing feature that uses the IOIS16 signal

from the PC Card to determine the data width of the I/O data transfer. Bit 1 is encoded as:

0 = Window data width is determined by I/O window 0 data-sizing bit, bit 0 (default).

1 = Window data width is determined by IOIS16.

R/W

I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if the I/O window 0 IOIS16 source bit

(bit 1) is set. Bit 0 is encoded as:

0 = Window data width is 8 bits (default).

1 = Window data width is 16 bits.

PCI1031PDV Datasheet(PDF) 65 Page - Texas Instruments

PCI1031PDV Datasheet(HTML) 65 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL