LT8335 datasheet(7/20 Pages) AD

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LT8338

Rev. 0

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TYPICAL PERFORMANCE CHARACTERISTICS

Load Step Response

(Pulse-Skipping Mode)

Load Step Response

(Burst Mode Operation)

1ms/DIV

8338 G19

ILOAD

100mA/DIV

500mA/DIV

VOUT

200mV/DIV

VINTVCC

20mV/DIV

1ms/DIV

8338 TPC20

ILOAD

100mA/DIV

500mA/DIV

VOUT

500mV/DIV

VINTVCC

20mV/DIV

PIN FUNCTIONS

VIN (Pin 1): Input Supply Pin. Bypass this pin to GND with

a low ESR ceramic capacitor of 0.1µF or greater. Place the

capacitor as close to the pin as possible.

BST (Pin 2): Top Switch Gate Driver Supply Pin. Tie a 0.1µF

capacitor between BST and SW as close as possible to the

pins to keep the trace length short.

SW (Pins 3, 4): Switch Node. Connect this pin to inductor,

and to the boost capacitor. SW is a high dV/dt node that

should be kept as compact as possible and away from high

impedance nodes.

VOUT (Pin 5): Output Voltage Pin. Bypass this pin to GND

with a low ESR ceramic capacitor of 4.7µF or greater. Place

the capacitor as close to the pin as possible. Additional

capacitance as required by specific applications must be

similarly closely placed. See the Applications and Physical

Layout sections for details. An 18:1 internal resistive

voltage divider provides feedback sensing of the output

voltage to the error amplifier.

SYNC/MODE (Pin 6): External Synchronization Input and

Light Load Operation Mode Selection Pin. This pin allows

five selectable modes for optimization of performance.

SYNC/MODE PIN INPUT

CAPABLE MODE(S) OF OPERATION

(1) GND or <0.14V

Burst

(2) 100k Resistor to GND

Burst/SSFM

(3) Float (Pin Open)

Pulse-Skipping

(4) INTVCC or >2.0V

Pulse-Skipping/SSFM

(5) External Clock

Pulse-Skipping/SYNC

where the selectable modes of operation are:

Burst = Low IQ, low output ripple operation at light loads

Pulse-Skipping = Skipped pulse(s) at light load (aligned to clock)

SYNC = Switching frequency synchronized to external clock

SSFM = Spread Spectrum Frequency Modulation for low EMI

RT (Pin 7): Switching Frequency Set Pin. Set the switch-

ing frequency with a resistor between this pin and GND.

Do not leave this pin open. In frequency synchronization

mode, use a resistor RT to program the frequency the

same as the synchronization signal.

EN/UVLO (Pin 8): Enable and Input Undervoltage

Lockout Pin. The LT8338 is shut down when this pin is

below 1V (typ), and is enabled when this pin is above

1.05V (typ). A resistor divider from VIN to GND pro-

grams a VIN threshold below which the LT8338 is shut

down. Tying this pin to GND shuts down operation and

reduces quiescent supply current to 0.2µA (max). Tie to

VIN if the shutdown feature is not used.

CTRL (Pin 9): Reference Input Pin. Tie the tap point of

a resistive voltage divider between INTVCC and GND to

this pin to set the error amplifier reference input to 1/18

of the desired system output voltage.

INTVCC (Pin 10): Internal 2.6V Regulator Pin. Bypass

this pin to GND with a low ESR ceramic capacitor of

2.2µF or greater. Place the capacitor as close to the pin

as possible. Set the output voltage (VOUT) by program-

ming the CTRL pin voltage via a resistive voltage divider

between INTVCC and GND. Use a minimum total resis-

tance of 1M to keep the divider’s contribution to the VIN

quiescent current to 2.6µA in shut down.

GND (Pin 11): Ground Pin. Connect this pin to system

ground and to the ground plane to achieve the best ther-

mal performance.

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