TPS65021 datasheet(11/45 Pages) TI

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TPS65021

SLVS613 – OCTOBER 2005

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected to

DEFDCDC1

a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set in

a range from 0.6 V to VINDCDC1 V

Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connected

DEFDCDC2

to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is set

in a range from 0.6 V to VINDCDC2 V

Input signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connected

DEFDCDC3

to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is set

in a range from 0.6 V to VINDCDC3 V

DCDC1_EN

VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.

DCDC2_EN

VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.

DCDC3_EN

VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.

LDO REGULATOR SECTION

VINLDO

I Input voltage for LDO1 and LDO2

VLDO1

Output voltage of LDO1

VLDO2

Output voltage of LDO2

LDO_EN

Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs

VBACKUP

Connect the backup battery to this input pin.

VRTC

Output voltage of the LDO/switch for the real time clock

VSYSIN

Input of system voltage for VRTC switch

DEFLD01

Digital input, used to set default output voltage of LDO1 and LDO2

DEFLD02

Digital input, used to set default output voltage of LDO1 and LDO2

CONTROL AND I2C SECTION

HOT_RESET

Push button input used to reboot or wake-up processor via RESPWRON output pin

TRESPWRON

Connect the timing capacitor to this pin to set the reset delay time: 1 nF

→ 100 ms

RESPWRON

Open drain System reset output

PWRFAIL

Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.

LOW_BAT

Open drain output of LOW_BAT comparator

INT

Open drain output

SCLK

Serial interface clock line

SDAT

I/O

Serial interface data/address

PWRFAIL_SNS

Input for the comparator driving the PWRFAIL output

LOWBAT_SNS

Input for the comparator driving the LOW_BAT output

TPS65021 Datasheet(PDF) 11 Page - Texas Instruments

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