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POWER SAVE MODE OPERATION

TPS65021

SLVS613 – OCTOBER 2005

DETAILED DESCRIPTION (continued)

pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The

VDCDC1 converter defaults to 3 V or 3.3 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is

tied to ground, the default is 3 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC1 pin is connected

to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the application

information section for more details.

The VDCDC2 converter defaults to 1.8 V or 2.5 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2

is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 2.5 V. When the DEFDCDC2 pin is

connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.

The VDCDC3 converter defaults to 1.3 V or 1.55 V depending on the DEFDCDC3 configuration pin. If

DEFDCDC3 is tied to ground the default is 1.3 V. If it is tied to VCC, the default is 1.55 V. When the DEFDCDC3

pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V. The

core voltage can be reprogrammed via the serial interface in the range of 0.8 V to 1.6 V with a programmable

slew rate. The converter is forced into PWM operation whilst any programmed voltage change is underway,

whether the voltage is being increased or decreased. The DEFCORE and DEFSLEW registers are used to

program the output voltage and slew rate during voltage transitions.

The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs of

which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged via

on-chip 300-

Ω resistors when the dc-dc converters are disabled.

During PWM operation, the converters use a unique fast response voltage mode controller scheme with input

voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output

capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is

turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The

current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the

adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the

inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel

rectifier and turning on the P-channel switch.

The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A

180

° phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90° shift to the VDCDC3

switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a

typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 3.3 V, the

VDCDC2 converter from 3.7 V to 2.5 V, and the VDCDC3 converter from 3.7 V to 1.5 V. The phase of the three

converters can be changed using the CON_CTRL register.

As the load current decreases, the converters enter the power save mode operation. During PSM, the converters

operate in a burst mode (PFM mode) with a switching frequency between half of the switching frequency and

switching frequency for one burst cycle. However, the frequency between different burst cycles depends on the

actual load current and is typically far less than the switching frequency with a minimum quiescent current to

maintain high efficiency.

In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode

the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM

is calculated as follows:

TPS65021 Datasheet(PDF) 21 Page - Texas Instruments

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