FXLS90120 datasheet(82/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

MOVEAVG[1] MOVEAVG[0]

Typical signal

sampling period

(Dependent on oscillator)

(µs)

Signal chain

moving average

Interpolation

8 Sample Moving Average

Disabled

128

8 Sample Moving Average

Disabled

Table 145. Signal chain moving average selection bits (MOVEAVG[1:0])...continued

Changes to these register bits reset the DSP data path. The contents of the SNSDATA_x

registers are not guaranteed until the DSP has completed initialization as specified in

Section 10.20. Reads of the SNSDATA_x registers and Sensor Data requests should be

prevented during this time.

11.2.26 Channel 0 user configuration #4 register (CH0_CFG_U4)

The Channel 0 user configuration #4 register is a user programmable read/write register

which contains channel-specific configuration information. This register is included in the

read/write array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$43

CH0_CFG_U4

RESET_OC

INVERT

OC_FILT[1:0]

PCM

ARM_CFG[2:0]

Unprogrammed OTP Value

Table 146. Channel 0 user configuration #4 register (CH0_CFG_U4)

11.2.26.1 Reset offset cancellation startup bit (RESET_OC)

When the reset offset cancellation startup bit is written to logic 1, the offset cancellation

startup is forced to phase 0 and follows the phase advancement as documented in

Section 11.6.4.6. The RESET_OC bit is cleared when the offset cancellation phase

reaches phase 1.

11.2.26.2 Signal inversion bit (INVERT)

The signal inversion bit provides the option to invert the polarity of the sensor signals as

shown in Table 147.

INVERT Acceleration

sensor data

Fixed pattern

self-test

Digital self-test

Analog self-test

Temperature

Positive

Self-Test:

Delta from Offset as

specified in Section 10

As shown in

Section 8.

As specified in

Section 11.2.27.1

Digital Self-Test

Activation results in

the values specified

in Section 10.8.

Negative

Self-Test:

Delta from Offset inverted

from the specified values

in Section 10.8 (Negative

Values)

As specified in

Section 11.7.2

Table 147. Signal inversion bit (INVERT)

FXLS9xxx0

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Product data sheet

Rev. 6 — 8 February 2021

82 / 247

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