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FXLS90120 Datasheet(PDF) 93 Page - NXP Semiconductors

Part # FXLS90120
Description  Single channel inertial sensor
PDF  247 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS90120 Datasheet(HTML) 93 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxx0
Single channel inertial sensor
RANGE[3]
RANGE[2]
RANGE[1]
RANGE[0]
Acceleration range
0
0
1
1
RESERVED
0
1
0
0
High
0
1
0
1
RESERVED
0
1
1
0
RESERVED
0
1
1
1
RESERVED
1
0
0
0
RESERVED
1
0
0
1
RESERVED
1
0
1
0
RESERVED
1
0
1
1
RESERVED
1
1
0
0
RESERVED
1
1
0
1
RESERVED
1
1
1
0
RESERVED
1
1
1
1
RESERVED
Table 173. Range indication bits (RANGE[3:0])...continued
11.2.36.2 Axis indication bits (AXIS[1:0])
The axis indication bits indicate the axes of sensitivity for the channel as shown in
Table 174.
AXIS[1]
AXIS[0]
Axis of sensitivity
0
0
X
0
1
Y
1
0
Z
1
1
RESERVED
Table 174. Axis indication bits (AXIS[1:0])
11.2.37 Self-test deflection storage registers
The self-test deflection registers are factory programmable OTP registers which contain
the nominal self-test values for the various self-tests at 25 °C. These registers are
included in the factory programmed OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$A2
CH0_STL_P_L
CH0_STL_P[7:0]
$A3
CH0_STL_P_H
CH0_STL_P[15:8]
$A4
CH0_STH_P_L
CH0_STH_P[7:0]
$A5
CH0_STH_P_H
CH0_STH_P[15:8]
$A6
CH0_STL_N_L
CH0_STL_N[7:0]
$A7
CH0_STL_N_H
CH0_STL_N[15:8]
Table 175. Self-test deflection storage registers
FXLS9xxx0
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
93 / 247



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