FXLS8967AF datasheet(33/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

Field

Description

SRC_ASLP

Auto-WAKE/SLEEP event status flag

0: A WAKE-to-SLEEP or SLEEP-to-WAKE system operating mode transition has not occurred.

1: A WAKE-to-SLEEP or a SLEEP-to-WAKE system operating mode transition has occurred.

Reading the

SYS_MODE register allows the host processor to determine if the transition direction

was from WAKE-to-SLEEP or SLEEP-to-WAKE:

• A WAKE-to-SLEEP transition is observed when no configured interrupt event occurs for a time

period (number of ODR periods) that equals the user-specified inactivity time limit programmed

in the

ASLP_COUNT_LSB and ASLP_COUNT_MSB registers. On expiry of configured time

period with no user specified activity, the system transitions to the user-specified SLEEP power

mode (

SENS_CONFIG2[sleep_pm]) and ODR (or decimation and idle time settings when Flexible

Performance mode is selected).

• A SLEEP-to-WAKE transition occurs when a configured interrupt event flag becomes

active. The interrupt event flag transitions to the user-specified WAKE power mode (

SENS_

CONFIG2[wake_pm]) and ODR (or decimation and idle time settings when Flexible Performance

mode is selected).

Notes:

• The SRC_ASLP event flag is cleared by reading the SYS_MODE register.

• The SRC_ASLP event flag is enabled when ASLP_COUNT ≥ 1 which also enables the Auto-

WAKE/SLEEP function. The SRC_ASLP flag is only operational when

INT_EN[ALSP_EN] = 1.

SRC_BOOT

System boot complete event flag

0: Boot sequence in process/not complete.

1: Boot sequence completed; FXLS8967AF is now ready to accept commands over the I2C or SPI

interfaces.

This flag is automatically set to 1 upon completion of the boot process and remains set until a POR,

soft reset, or exit from Hibernate mode event occurs.

When BT_MODE = GND: Boot interrupt is generated in INT1/MOT_DET pin by default. This event

flag may be configured to generate an interrupt on either the INT1 or INT2 pin depending on the

mapping selected in

INT_PIN_SEL. When this event flag is enabled as an interrupt output, either the

INT1 or INT2 (depending on the setting made in

INT_PIN_SEL register) pin is pulsed once with a

width of TBOOT1 µs when the boot process completes.

When BT_MODE = VDD: The INT2/BOOT_OUT pin is pulsed once with a duration of TBOOT2 ms when

the boot process completes. The pulse is active low (open-drain output); an external pull-up resistor is

required.

Notes:

• When BT_MODE = GND, after a POR or exiting Hibernate mode, the polarity of the BOOT pulse

is default Active High because any I2C write to the

SENS_CONFIG4[INT_POL] fails until the boot

process has completed.

• After a Soft Reset, the INT_POL, INT_PP_OD, and INT_PIN_SEL register settings are

not reset and maintain their previous values. As a result, an I2C or SPI write to the

SENS_

CONFIG4[(INT_PP_OD and INT_POL bits)] and INT_PIN_SEL[BOOT_INT2] bits before the Soft

Reset determines the logic polarity, output driver type, and INT1/2 pin mapping of the subsequent

Boot pulse.

• It is not possible to observe the state of the SRC_BOOT bit at '0' over the I2C or SPI interfaces as

read and write operations fails until the boot process has completed.

Table 22. INT_STATUS register (address 00h) bit description...continued

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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