FXLS8967AF datasheet(59/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

Field

Description

DRDY_INT2

Data-ready interrupt routing

0: If data-ready interrupt routing is enabled, the interrupt signal is routed to INT1 pin.

1: If data-ready interrupt routing is enabled, the interrupt signal is routed to INT2 pin.

BUF_INT2

Output buffer interrupt routing (

BUF_OVF | BUF_WMRK | BUF_GATE_ERR):

0: If output buffer interrupt routing is enabled, the interrupt signal is routed to INT1 pin. (default)

1: If output buffer interrupt routing is enabled, the interrupt signal is routed to INT2 pin.

SDCD_OT_INT2

SDCD outside of thresholds event interrupt routing

0: If SDCD outside of thresholds event interrupt routing is enabled, the interrupt signal is routed to

INT1 pin.

1: If SDCD outside of thresholds event interrupt routing is enabled, the interrupt signal is routed to

INT2 pin.

SDCD_WT_INT2

SDCD within thresholds event interrupt routing

0: If SDCD within thresholds event interrupt routing is enabled, the interrupt signal is routed to INT1

pin.

1: If SDCD within thresholds event interrupt routing is enabled, the interrupt signal is routed to INT2

pin.

ORIENT_INT2

ORIENT event interrupt routing

0: If ORIENT event interrupt routing is enabled, the interrupt signal is routed to INT1 pin.

1: If ORIENT event interrupt routing is enabled, the interrupt signal is routed to INT2 pin.

ASLP_INT2

Auto-WAKE/SLEEP event interrupt routing

0: If Auto-WAKE/SLEEP event interrupt routing is enabled, the interrupt signal is routed to INT1 pin.

1: If Auto-WAKE/SLEEP event interrupt routing is enabled, the interrupt signal is routed to INT2 pin.

BOOT_INT2

BOOT event interrupt routing

If a user operation sets BOOT_INT2 before issuing a soft reset command, the setting is maintained

through the reset sequence (the setting is lost if VDD supply is removed).

0: If BOOT event interrupt routing is enabled, the interrupt signal is routed to INT1 pin.

1: If BOOT event interrupt routing is enabled, the interrupt signal is routed to INT2 pin.

Note: When BT_MODE = VDD, this bit is ignored; the BOOT interrupt is internally mapped to the

INT2/BOOT_OUT pin (fixed setting).

WAKE_OUT_INT2

WAKE power state interrupt routing

0: If WAKE power state interrupt routing is enabled, the WAKE power state output is routed to INT1

pin.

1: If WAKE power state interrupt routing is enabled, the WAKE power state output is routed to INT2

pin.

Table 74. INT_PIN_SEL register (address 21h) bit description

15.23 OFF_X, OFF_Y, OFF_Z registers (addresses 22h to 24h)

Registers 22h to 24h (OFF_X/Y/Z) can be used to realign the zero-g position of the X-,

Y-, and Z-axes after PCB assembly. The registers are 8 bit, 2's complement providing an

offset adjustment range of –128 to 127.

Equation 2 determines the effective offset value in mg, set by each of the OFF_X/Y/

Z registers. The equation is an X-axis example, with the other axes offsets set in an

identical manner.

OFF_X

(2)

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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