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FXLS8967AF Datasheet(PDF) 80 Page - NXP Semiconductors |
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FXLS8967AF Datasheet(HTML) 80 Page - NXP Semiconductors |
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80 / 98 page  NXP Semiconductors FXLS8967AF 3-Axis Low-g Accelerometer 16 Application information 16.1 System connections FXLS8967AF connects to a host processor through an I2C or SPI interface. Figure 19 to Figure 24 show the recommended circuit connections. 16.2 Typical application circuits X7R or X5R ceramic capacitors are recommended for VDD supply decoupling. A 1 µF capacitor in parallel with a 0.1 µF is recommended as a starting point per the NXP EMC test standard. These capacitors should be placed as close to the VDD supply pin as practical. The values of the capacitors can be changed to suit the EMC performance requirements of the application. aaa-040829 R4 C2 1.0 µF C1 0.1 µF R1 R2 1 2 3 4 5 10 9 8 7 6 VDD VDD VDD BT_MODE GND INTF_SEL INT1/MOT_DET SPI_CS_B/WAKE_UP INT2/EXT_TRIG/BOOT_OUT INT1 WAKE_UP INT2/EXT_TRIG SA0/SPI_MISO I2C_SA0 I2C_SDA I2C_SCL SDA/SPI_MOSI SCL/SCLK R3 Figure 19. Typical Application Circuit #1 – I2C mode Notes: • Resistors R1 and R2 are not needed if the interrupt output driver type is configured for push-pull operation (default). • If either the INT1 or INT2 pins are not used in the application, leave them unconnected. • The required pull-up resistor values for R3 and R4 are dependent on several factors including the I2C clock frequency, bus pull-up voltage, and the total parasitic trace + device capacitances. A suggested starting point is 4.7 kΩ for Standard and Fast modes. • The external trigger function can be used to initiate a single shot measurement of the XYZ acceleration and temperature data. This mode is useful for synchronizing measurements with an external system or for creating user-specific ODRs. The measurement is triggered on the rising edge of the EXT_TRIG signal. aaa-040830 C1 0.1 µF R1 R2 1 2 3 4 5 10 9 8 7 6 VDD VDD VDD BT_MODE GND INTF_SEL INT1/MOT_DET SPI_CS_B/WAKE_UP INT2/EXT_TRIG/BOOT_OUT INT1 WAKE_UP INT2/EXT_TRIG SA0/SPI_MISO MOSI MISO SCLK SDA/SPI_MOSI/SPI_DATA SCL/SCLK C2 1.0 µF Figure 20. Typical Application Circuit #2 – SPI 4-wire mode FXLS8967AF All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Objective data sheet Rev. 1 — 27 April 2021 80 / 98 |
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