FXLS8967AF datasheet(82/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

aaa-040834

0.1 µF

R2 (optional)

(optional)

VDD

BT_MODE

GND

INTF_SEL

INT1/MOT_DET

SPI_CS_B/WAKE_UP

INT2/EXT_TRIG/BOOT_OUT

MOT_DET

SPI_CS_B/WAKE_UP

BOOT_OUT

DNC

SDA/SPI_MOSI/SPI_DATA

SCL/SCLK

SPI_DATA

SCLK

1.0 µF

Figure 24. Typical Application Circuit #6 - Motion detection mode (with SPI 3-wire interface, software enabled)

Notes:

• External resistor R2 is not needed if the BOOT_OUT and MOT_DET pins are tied

together (wired AND configuration).

• A suggested pull-up resistance range is 1 MΩ to 2.5 MΩ for both R1 and R2 to

minimize the power dissipated in the resistor when the line is pulsed low. When

BT_MODE is set to VDD (enabling motion detection mode), both the MOT_DET and

BOOT_OUT pins become open-drain output driver types. MOT_DET also functions as

a CMOS input and is used by the host system to power-manage FXLS8967AF.

• When BT_MODE = VDD, the default motion detection parameters are automatically

loaded into the device after a POR/BOR event occurs; no configuration via I2C or SPI is

needed if the default parameters are used in the application.

• See Section 13.2 and Section 13.4 for more details on 3-wire SPI mode. In motion

detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only

the default LPM mode should be used.

16.3 Power supply considerations

NXP recommends that VDD be sourced from a low noise linear supply regulator (LDO).

When using a switch mode supply, the recommended minimum voltage is 1.8 V

(nominal), providing headroom for supply noise and ripple rejection. This headroom

ensures that the device meets its performance specifications while also preventing a

BOR/POR event from occurring when operated on a noisy supply rail.

FXLS8967AF contains a POR generator. This circuit resets the digital logic and restores

all register content to the default values shown in Table 20 after applying VDD ≥ 1.71 V, or

after a soft reset command is issued by setting

SENS_CONFIG1[RST] = 1.

Note: The host system must wait for a nominal time period of TBOOT1/2 ms after

applying VDD ≥ 1.71 V, or after issuing a soft reset command, to allow enough time for

FXLS8967AF to complete its internal boot sequence and be ready for communication

over the I2C or SPI interfaces.

When the BT_MODE pin is low, with

INT_EN[BOOT_DIS] = 0, the host system can wait

until the active edge of a TPULSE-BOOT1 µs pulse is observed on the INTx pin (determined

INT_PIN_SEL[BOOT_INT2]) indicating completion of the boot sequence. When

the BT_MODE pin is logic high, the INT2 pin is configured as an open-drain output

(BOOT_OUT) that pulses low for TPULSE-BOOT2 ms after the boot sequence completes.

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

82 / 98

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