FXLS8967AF datasheet(5/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

Symbol

Description

INT2 / EXT_TRIG /

BOOT_OUT

6 Mode-dependent multifunction I/O pin 2.[2]

BT_MODE = VDD: Open-drain[4] output signaling the device

boot process has completed. This pin is typically connected to

MOT_DET in a wired-AND configuration; a pull-up resistor is

required.

BT_MODE = GND: Programmable interrupt output pin 2[5] /

External measurement trigger input. This pin should be left

unconnected if unused in the application circuit.

SPI_CS_B / WAKE_UP

7 SPI chip select input, active low / Hibernate mode wake-

up pin.[6] The WAKE_UP function is only available when

BT_MODE = GND.

INT1 / MOT_DET

8 Mode-dependent multifunction I/O pin 1.[7]

BT_MODE = GND: Programmable interrupt output pin 1.[5]

This pin should be left unconnected if unused in the application

circuit.

BT_MODE = VDD: MOT_DET multifunction I/O.[4] The host

MCU sets this pin high through a pull-up resistor to enable

motion detection, and drives it low for greater than TMOT-HIB

ms to disable motion detection and enter Hibernate mode.

FXLS8967AF will pulse the line low for TPULSE-MOT ms after

motion is detected. This line may also be used to select

the motion detection threshold. See Section 14 for more

information.

INTF_SEL

9 Device interface mode selection pin.

VDD: SPI interface mode [3]

GND: I2C interface mode

GND

10 Supply return connection.

Table 3. Pin descriptions...continued

[1]

BT_MODE state is latched after POR.

[2]

Under Hibernate mode, pin configuration is High Impedance.

[3]

3-wire SPI mode may be selected in

SENS_CONFIG1[SPI_M]; 3-wire operation is also possible by directly connecting

the SPI_MISO and SPI_MOSI pins together on the PCB.

[4]

An external pull-up resistor is required on this pin when BT_MODE = VDD.

[5]

This pin is configurable as either an input or output (push-pull or open-drain/open-source output type), but defaults to a

push-pull output after POR, or after exiting Hibernate mode.

[6]

Under Hibernate mode, pin configuration is High Impedance (when BT_MODE = VDD) and CMOS Input (when BT_MODE

= GND).

[7]

Under Hibernate mode, pin configuration is High Impedance (when BT_MODE = GND) and CMOS Input (when

BT_MODE = VDD).

FXLS8967AF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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