FXLS8967AF datasheet(43/98 Pages) NXP

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NXP Semiconductors

FXLS8967AF

3-Axis Low-g Accelerometer

Field

Description

6 to 2

BUF_GATE_CNT[4:0]

The BUF_GATE_CNT field contains the number of OOR periods that have elapsed since the

BUF _GATE_ERR flag was asserted.

This buf_gate_cnt field is reset to 0 after any of the following actions:

1. The host reads out the entire contents of the output buffer such that

BUF

STATUS[BUF_CNT[5:0]] = 0.

2. The host flushes (clears) the output buffer by setting

BUF _CONFIG2[BUF _FLUSH] = 1.

3. Disable the output buffer by setting

BUF CONFIG1[BUF _MODE[1:0]] = 00b, which also

clears the buffer contents.

4. Transitioning FXLS8967AF from Standby to Active mode. which also clears the buffer

contents.

1 to 0

SYS_MODE[1:0]

The current system operating mode

00b: Standby mode (default mode after a POR or soft reset event when BT_MODE = GND)

01b: WAKE mode (default mode after a POR or soft reset event when BT_MODE = VDD and

MOT_DET = 1)

10b: SLEEP mode

11b: EXT_TRIG mode (this mode is unavailable when BT_MODE = VDD)

Notes:

• When external trigger mode is enabled (with SENS_CONFIG4[INT2_FUNC] = 1), while the

device is waiting for a trigger event to occur, SYS_MODE[1:0] is set to 11b. When the trigger

is received, SYS_MODE[1:0] is set to 01b while the measurement is being made, and then

change back to 11b and remain there until the next trigger signal is received.

• When INT_EN[WAKE_OUT_EN] = 1, and SYS_MODE[1:0] = 01b (WAKE), the device outputs

either a logic '1' or '0' on either the INT1 or INT2 pins, depending on the settings made in

INT_

PIN_SEL[WAKE_OUT_INT2] and SENS_CONFIG4[INT_POL].

• When entering the WAKE, SLEEP, or EXT_TRIG modes, the internal debounce counters for

the ORIENT, SDCD_WT, and SDCD_OT event functions are automatically reset.

Table 46. SYS_MODE register (address 14h) bit description...continued

15.11 SENS_CONFIG1 register (address 15h)

Bit

Name

RST

ST_AXIS_SEL[1:0]

ST_POL

SPI_M

FSR[1:0]

ACTIVE

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 47. SENS_CONFIG1 register (address 15h) bit allocation

FXLS8967AF

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Objective data sheet

Rev. 1 — 27 April 2021

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