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IMX6SDLCEC Datasheet(PDF) 132 Page - NXP Semiconductors

Part # IMX6SDLCEC
Description  i.MX 6Solo/6DualLite Applications Processors for Consumer Products
PDF  169 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX6SDLCEC Datasheet(HTML) 132 Page - NXP Semiconductors

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018
132
NXP Semiconductors
Electrical Characteristics
UART IrDA Mode Receiver
Figure 98 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 90 lists
the receive timing characteristics.
Figure 98. UART IrDA Mode Receive Timing Diagram
4.11.21 USB HSIC Timings
This section describes the electrical information of the USB HSIC port.
NOTE
HSIC is DDR signal, following timing spec is for both rising and falling
edge.
4.11.21.1 Transmit Timing
Figure 99. USB HSIC Transmit Waveform
Table 90. IrDA Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
UA5 Receive Bit Time1 in IrDA mode
1
The UART receiver can tolerate 1/(16
x Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16
x Fbaud_rate).
tRIRbit
1/Fbaud_rate
2 - 1/(16 x F
baud_rate)
2 F
baud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
1/Fbaud_rate + 1/(16 x Fbaud_rate)—
UA6 Receive IR Pulse Duration
tRIRpulse
1.41
μs
(5/16) x (1/Fbaud_rate)—
Table 91. USB HSIC Transmit Parameters
Name
Parameter
Min
Max
Unit
Comment
Tstrobe
strobe period
4.166
4.167
ns
—
Todelay
data output delay time
550
1350
ps
Measured at 50% point
Tslew
strobe/data rising/falling time
0.7
2
V/ns
Averaged from 30% – 70% points
Bit 1
Bit 2
Bit 0
Bit 4
Bit 5
Bit 6
Bit 7
UARTx_RX_DATA
(input)
Bit 3
Start
Bit
STOP
BIT
Possible
Parity
Bit
UA5
UA5
UA5
UA5
UA6
USB_H_STROBE
USB_H_DATA
Todelay
Tstrobe
Todelay



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