DA14682 datasheet(39/459 Pages) DIALOG

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Datasheet

Revision 3.3

6-Feb-2020

CFR0011-120-00-FM Rev 5

39 of 459

DA14682

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4.1.3 Switching from DC-DC to LDOs

If the converter is in idle mode it will check each output

every 2, 4, 8 or 16 clock cycles of the 16 MHz clock

and if it finds that one or more output voltages are too

low it will commence a charge cycle. It will then sort the

outputs that require charging, according to a configur-

able

sequence

(i.e.

DCDC_CTRL_0[DCDC_PRIORITY]) and handle each

output in turn. The first step is then to connect the

inductor to the battery voltage and the required output

and wait for the current in the inductor to reach a cer-

tain maximum (which is automatically adjusted

depending on the load current). The next step is to

switch the inductor from VBAT1 to ground and dis-

charge the current to zero.

In the case of the external power supply dropping down

to 2.4 V, and of course upon the load on each output, a

time-out on the charging cycle might occur. Hence the

output rail is not charged as expected and maybe the

DCDC converter cannot continue supplying this output

with the required power.

As soon as one of the switches is activated, a counter

starts running. If the switch is active for more than

DCDC_CTRL_1[DCDC_TIMEOUT] time then a time

out event is generated. A counter gathers the time out

events, compares the current value to a programmable

threshold

(DCDC_CTRL_3[DCDC_TIMEOUT_IRQ_TRIG]) and

issues an interrupt to the CPU indicating the phasing

out situation of the converter or immediately switches

to the LDOs. Whether the decision is to be taken by the

hardware circuitry or SW over the interrupt service rou-

tine is user programmable.

A separate counter gathers the successive charge

events and compared to a programmable threshold

(DCDC_CTRL_3[DCDC_TIMEOUT_IRQ_RES]

clears the time out event counter before an interrupt is

triggered. In this way, any short periodic stress inter-

vals for the DCDC will not result to switching to the

LDOs automatically.

The respective LDOs should be switched on before

disabling the DCDC converter (i.e. just before entering

a sleep mode). Each power rail (except Vcont and

Vsys) is covered by both a DCDC output and an LDO.

To switch off the DCDC, the user must enable the

LDO_IO_RETx (if external components need to stay

powered). If Vradio is required on, then LDO_RADIO

should be activated as well.

4.1.4 PMU configurations in Sleep modes

Every power line can be supplied by either a DC-DC

output or an LDO. Only Vcont and Vsys is not powered

by a DC-DC output. There is quite a number of different

ways of configuring the PMU to supply the internal rails

as well as external devices, while in sleep mode,

depending on the load, the sleep time etc. The Vsys

rail might or might not be used for supplying an exter-

nal device via pin V33. In the first case, a stable Volt-

age level might be needed hence the LDO_VBAT_RET

has to be used, a sample-and-hold type of LDO which

samples the bandgap voltage on a regular basis and

regulates accordingly. The regular wake-up is based

on the SLEEP_TIMER_REG value. In the latter case,

no precise voltage is needed on the V33, hence the

LDO_RET_clamp should be used which is not requir-

ing any sampling of the bandgap reference voltage,

and the average sleep current is not affected.

Figure 20: LDO_VBAT_RET loadstep 0 to 10mA (Cload=10uF)

DA14682 Datasheet(PDF) 39 Page - Dialog Semiconductor

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