DA14682 datasheet(74/459 Pages) DIALOG

74 / 459 page

Datasheet

Revision 3.3

6-Feb-2020

CFR0011-120-00-FM Rev 5

74 of 459

DA14682

Bluetooth Low Energy 5.0 SoC with Enhanced Security and FLASH

FINAL

12.1.3 SPI modes

The Quad SPI Controller (QSPIC) supports the follow-

ing SPI standards:

• Single: Data transfer via two unidirectional pins.

Note 2:

The QSPIC supports communication to any single/dual or

Quad SPI FLASH memory. Contrary to the Standard SPI

interface, the supported Single SPI interface does not sup-

port the bus modes 1 and 2, does not support full-duplex

communications and does not support any SPI slave mode.

• Dual: Data transfer via two bidirectional pins.

• Quad: Data transfer via four bidirectional pins.

12.1.4 Access modes

The access to a serial FLASH connected to the QSPI

can be done in two modes:

• Auto mode

• Manual mode

These modes are mutually exclusive. The serial

FLASH can be controlled only in one of the two modes.

The registers which control the mode of operation can

be used at any mode.

In auto mode, 3-bytes and 4-bytes addressing modes

are

supported.

With

QSPIC_CTRLMODE_REG

[QSPIC_USE_32BA]=0, up to 16 MBytes QSPI (3-

bytes

addressing)

can

accessed.

QSPIC_USE_32BA=1, the 4-bytes addressing is ena-

bled for accessing up to 32 Mbyte QSPI FLASH.

Auto mode

In auto mode a read access from the serial FLASH

memory is fully transparent to the CPU. A read access

at the interface is translated by the QSPIC into the

respective SPI bus control commands needed for the

FLASH memory access.

When the Auto Mode is disabled, any access (reading

or writing) will be ignored. When the Auto Mode is ena-

bled, only read access is supported. A write access

causes hard fault. A read access can be single access,

incremental burst or wrapping burst. Wrapping burst is

supported even when the FLASH device doesn’t sup-

port any special instruction for wrapping burst. A spe-

cial read instruction can be used in the case of a

specific (programmable) wrapping burst access. When

a FLASH supports a special instruction for wrapping

burst access, this feature reduces access time (less

wait states). For maximizing the utilization of the bus

and minimizing the number of wait states, it is recom-

mended to use burst accesses. However, non-sequen-

tial random accesses are supported with the cost of

more wait states.

Manual Mode

In manual mode the FLASH memory is controlled via a

FLASH memory can be programmed using the register

file. Moreover, the mode of interface (SPI, Dual SPI,

Quad SPI) and the mode of operation (Auto or Manual

Mode) can be configured via this register file. The reg-

ister file supports the following data sizes for reading

and writing accesses: 8-bits, 16-bits and 32 bits.

12.1.5 Endianess

The QSPIC operates in little-endian mode. For 32-bit

or 16 bit access (for read and write operations) to a

serial FLASH memory, the least-significant byte comes

first. For 32-bit access the byte ordering is: data [7:0],

data [15:8], data [23:16], data [31:24] while for 16-bit

access the byte ordering is: data [7:0], data [15:8].

12.1.6 Erase Suspend/Resume

The QSPI FLASH can be used for Data Storage, com-

bining the EEPROM functionality + Program storage in

one single device.

For this purpose the QSPI ERASE/SUSPEND ERASE

RESUME commands are automatically executed as

shown in Figure 46.

To store data in QSPI FLASH, execution from QSPI

must temporary be stopped by running directly from

RAM or from a cached program part. The sector desig-

nated for storage must be erased first in case it con-

tained data already.

The process is implemented in a HW FSM and con-

sists of the following steps:

1. The controller is in Auto mode and read requests

are served. The Erase procedure is initiated by

setting QSPIC_ERASE_EN=1. The address of

the sector that will be erased, is defined at

QSPIC_ERS_ADDR. When an Erase procedure

is requested, the controller jumps to state 2.

2. Read requests are still served. As soon as the

Read requests stop (also possible due to late

bus master change, e.g DMA) and there is no

any new Read request for a number of AHB

clock cycles equal to QSPIC_ERSRES_HLD,

then

QSPIC_WEN_INST

and

QSPIC_ERS_INST instructions are sent to the

FLASH. The QSPIC_RESSUS_DLY counter is

started and the controller jumps to state 3.

3. Erasing is in progress in FLASH and the QSPI

controller waits until one of the following events

occur:

• A status check request. This request can be

forced by writing QSPIC_CHCKERASE_REG.

The QSPI controller will then read the status of

the FLASH memory and check if erasing has

finished. Reading of the status is delayed by

QSPIC_RESSTS_DLY cycles or by

QSPIC_RESSUS_DLY cycles. The first is

based on the clock of the SPI bus, while the lat-

ter on an internal 222 KHz clock. The selection

between the two delays is configured by

QSPIC_STSDLY_SEL bit. If erasing has fin-

ished, the QSPI controller returns to the normal

operation (state 1) and sets

QSPIC_ERASE_EN= 0, otherwise it remains at

DA14682 Datasheet(PDF) 74 Page - Dialog Semiconductor

DA14682 Datasheet(HTML) 74 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL