DA14682 datasheet(90/459 Pages) DIALOG

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Datasheet

Revision 3.3

6-Feb-2020

CFR0011-120-00-FM Rev 5

90 of 459

DA14682

Bluetooth Low Energy 5.0 SoC with Enhanced Security and FLASH

FINAL

True Random Number Generator

(TRNG)

The TRNG is a non-deterministic Random Number

generator used to provide the seed for encryption pro-

cesses.

Its output can be used as entropy input for a FIPS 140-

2 approved deterministic random number generation

process which is handled by SW and HW accelerators

of the DA14682.

The TRNG contains oscillator rings in digital logic

which combined create metastability on a Flip-Flop

eventually being the source of the entropy bits.

Features

• Optional NIST SP800-90A Hash_DRBG post pro-

cessing using SHA-256 function using the on-chip

HW accelerators

• Random numbers access through 32x32 bits FIFO

on AHB bus

• Dedicated TRNG_IRQ Interrupt line

• Start-up time 512 pclk cycles per 32 random bits

• Clock enable signals for optimal power saving

16.1 ARCHITECTURE

Figure 57 shows the TRNG block diagram.

The TRNG comprises a number oscillator rings con-

sisting of several inverters each. The output of the

oscillator rings are accumulated in a shift register for

whitening before being stored in a 32x32 bits deep

FIFO. The oscillator rings are enabled when the

TRNG_CTRL_REG[TRNG_ENABLE] is set and as

long as the FIFO is not full.

The 32-bit random numbers are accessible via an AHB

interface while the registers are accessible via the

APB32 interface.

16.2 PROGRAMMING

There is a simple sequence of steps that need to be

followed to program the TRNG engine:

1. Set CLK_AMBA_REG[TRNG_CLK_EN]=1 to

enable the AHB bus access

2. Set TRNG_CTRL_REG[TRNG_MODE]=0 to

selects the ring oscillators rather then a pseudo

random generator

3. Set TRNG_CTRL_REG[TRNG_ENABLE]=1 to

start the random number generation. This signal

is ignored when the FIFO is already full

4. Poll TRNG_FIFOLVL_REG which provides the

amount of data in the FIFO, or wait for the

TRNG_IRQ

5. Read the random number from the TRNG FIFO

at address 0x40040000 (TRNG_M)

6. To save power, set TRNG_CLK_EN=0 and set

TRNG_ENABLE=0. The FIFO can only be

accessed if TRNG_CLK_EN=1

Note that, all signals are handled following the little-

endian format. That means that the Least Significant

Byte (LSB) is stored at the lowest address.

16.2.1 Latency

After TRNG_CTRL_REG[TRNG_ENABLE] is set to 1,

it takes 512 pclk clock cycles/FIFO entry. So for 32

FIFO entries 512x32 = 16K pclk clock cycles or 1 ms if

the 16 MHz clock is used.

Figure 57: TRNG block diagram

TRNG

Ring Oscillators

. . .

Shift

FIFO (32b x 32)

Control & Status

Registers

APB Interface

AHB Interface

AHB

APB32

TRNG_IRQ

ahb_clk

CLK_AMBA_REG[TRNG_CLK_ENABLE]

TRNG_CLK

TRNG_CTRL_REG[TRNG_ENABLE]

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