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Datasheet

Revision 3.3

6-Feb-2020

CFR0011-120-00-FM Rev 5

40 of 459

DA14682

Bluetooth Low Energy 5.0 SoC with Enhanced Security and FLASH

FINAL

The overview of the power configurations is presented

in Table 10:

There are many ways of configuring the PMU, how-

ever, there are two main sleep configuration options

that cover almost all cases:

1. Power Configuration #1: This configuration is

ideal for a stand-alone system running from OTP

and without external components supplied by

the PMU during sleep or as a “shipping mode”

where no external components are hooked up

on V33 and components on V18/V18P are pow-

ered off. The Vsys rail is powered by the

LDO_RET(Clamp) hence a voltage ~2V is to be

observed at the V33 pin. The Vext and Vflash

are switched off. Finally, the Vcore is powered by

the LDO_SLEEP at lower than normal voltage

level to reduce leakage. Please note that, using

the RCX as the sleep clock in this mode is not

recommended because the RCX is powered by

Vsys which is not a stable voltage. The RCX fre-

quency is voltage dependent, so if voltage

changes sleep clock behaviour will also change.

This applies to Deep Sleep and Hibernation.

2. Power Configuration #2: This configuration is

the same as #1 but Vsys is now powered by

LDO_VBAT_RET, which is a sample and hold

LDO, thus guaranteeing a stable voltage on this

rail. This enables connecting external compo-

nents on the V33 pin of the system.

SLEEP_TIMER_REG has to be programmed

with a value to trigger the period wakeup of the

Bandgap. This is the recommended configura-

tion for systems with external components on

1.8V and/or 3.3V rails kept alive while the

DA14682 is in Extended Sleep mode.

4.1.5 Wake/Power up - Sleep Timing

There are two HW controlled FSMs which run at

power/wake up and when going to sleep as explained

in section 3.4.1 and section 3.4.2 respectively. Their

timing regarding the enabling/disabling of the various

resources of the PMU is explained in Figure 21 and

Figure 22:

In the case of powering up the system, the HW FSM as

depicted in Figure 3, enables the various LDOs while

Table 10: Sleep PMU configurations

Power

Rail

Power

Configuration #1

Power

Configuration #2

Vcont

always on powered by LDO_RET

Vsys

LDO_RET(CLAMP) LDO_VBAT_RET

Vflash

OFF

LDO_IO_RET

Vext

OFF

LDO_IO_RET2

Vcore

LDO_SLEEP

Vradio

OFF

Figure 21: Wake/Power-Up timing and PMU operations

Start V33

Start VDD 1V8 P

Start VDD 1V 8

Start VDD _CO RE

Sw itch

to RC16

CLK

RUNNIN G SW ...

LDO_VBAT

LDO_CO RE

LDO_IO 2

LDO _IO

DCDC_1V8

DCDC_1V8P

DCDC_1V2

DCDC_1V4

SLEEP

Wake Up Event

F ilter

WUP

LDO _IO 2_RET

LDO_IO_RET

LDO _VBAT_RET

W ake U p P rocess

controlled

Pow er U p

Wake U p

HW FSM

XTAL32K(30.5us) / RCX (87.7us)

RC32 (31.2us)

RC16 untrim m ed (~100ns)

RC16 trim m ed (~60ns)

RC16_Enable

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