DA14682 datasheet(66/459 Pages) DIALOG

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Datasheet

Revision 3.3

6-Feb-2020

CFR0011-120-00-FM Rev 5

66 of 459

DA14682

Bluetooth Low Energy 5.0 SoC with Enhanced Security and FLASH

FINAL

9AMBA Bus

The DA14682 is equipped with a multi-layer AMBA bus

which enables parallel data paths between different

masters and slaves. The bus matrix comprises 2 main

busses:

• AHB-CPU bus where the Cache, or the CPU can be

masters

• AHB-DMA bus where the DMA the OTP Controller

and the AES/HASH DMA can be masters

Features

• Enables data transfers from peripherals to memory

while executing code from OTP or QSPI FLASH

• Enables data transfers from RAM to BLE while exe-

cuting code from OTP or QSPI FLASH

• Provides programmable master priority on AHB-

CPU bus

• Provides programmable ICM priority for the con-

nected Slaves

• Enables AHB access of the CPU at the cache RAM

if no cache functionality is required

There are six slaves which are sitting behind intercon-

nection multiplexers (ICMs), namely:

• Memory controller which controls the DataRAM and

the ROM cells

• QSPI FLASH memory controller and memory

• 16-bit APB peripheral registers

• AHB register files for the rest of the resources as

well as the TRNG RAM

• 32-bit APB peripheral registers

• Cache controller which enables AHB access of the

Figure 40: AMBA Bus architecture

Secure Channel

Ctrl.

Data RAM cells

Cache

AHB Reg. Files

BLE reg

CRYPTO reg

OTPC reg

ECC reg

QSPI FLASH

Mem.Ctrl.

Legend:

AHB/APB Master interface.

AHB/APB Slave interface

AHB/APB Bus

AHB Interconnection Matrix (ICM)

Arm

Cortex-M0

QSPIC reg

Re-

map

Addr0

TRNG RAM

ROM

AES/Hash DMA

DMA

APB-16 Bridge

AON Reg. Files

CRG reg

WakeUp reg

BLE

Periph. Reg. Files

UART reg

SPI reg

etc.

Radio Reg. Files

RF reg

COEX reg

Sys Reg. Files

WDG reg

DMA reg

etc.

OTP Mem

patch

APB‐32 Bridge

Audio Reg. Files

PCM reg

etc

OTPC

OTPC reg

Remap_

RAMS

TRNG Reg. File

ECC

ROM Ctrl.

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