DA14682 datasheet(68/459 Pages) DIALOG

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Datasheet

Revision 3.3

6-Feb-2020

CFR0011-120-00-FM Rev 5

68 of 459

DA14682

Bluetooth Low Energy 5.0 SoC with Enhanced Security and FLASH

FINAL

Memory Controller

The Memory controller is responsible for the interface

of the memory cells with the masters of the system

requesting for access. It comprises an arbiter which

allows for a configurable priority level between the 3

main masters of the RAM. The memory controller also

allows for the actual physical sequence of the RAM

cells in a continuous memory space enabling activation

of just the required amount of DataRAM thus saving on

power.

Features

• Five different RAM cells with retention capability

(one 8 kB, one 24 kB and three 32 kB)

• Full flexibility of re-arranging the first 3 RAM cells in

a continuous RAM space starting at 0x7FC0000

• Arbitration between the AHB masters (CPU or

DMAs) the BLE core and the ECC

• Retainable configuration of the RAM cells sequence.

The Shuffle_RAM word in the OTP header encodes the

sequence of the RAM cells. This is described in Table

25:

Selecting the appropriate shuffle value, the minimum

required memory space can be left retained during

sleep modes hence reducing the sleep power dissipa-

tion.

The Memory Controller contains an Arbiter which con-

nects to the following busses:

• ICM which multiplexes the CPU or the DMA access.

This interface is capable of operating at maximum

96MHz

• BLE Memory I/F: this is a memory interface from the

BLE 4.2 Core directly accessing the RAM used as

exchange memory (TX/RX descriptors etc.). This

interface is always operating at 16MHz.

• ECC Memory I/F: this is a memory interface from the

Elliptic Curve Crypto block directly accessing the

RAM used as crypto shared memory. This interface

is capable of operating at maximum 96MHz.

The Arbiter implements the priority scheme as depicted

in Figure 42:

Figure 41: Memory Controller Block Diagram and environment

Memory Controller

DataRAM 1

8KB

DataRAM 2

24KB

DataRAM 3

32KB

SYS_CTRL_REG[REMAP_RAMS]

BLE 4.2

BLE - AHB

BLE Mem I/F

Sequence

Config

DataRAM 4

32KB

DataRAM 5

32KB

0x7FD0000

0x7F

D800

ECC

ECC Mem I/F

Table 25: DataRAM cells sequence

Value

Cell

Addess

Size (kB)

0x0

DataRAM1

0x7FC0000

DataRAM2

0x7FC2000

DataRAM3

0x7FC8000

0x1

DataRAM2

0x7FC0000

DataRAM1

0x7FC6000

DataRAM3

0x7FC8000

0x2

DataRAM3

0x7FC0000

DataRAM1

0x7FC8000

DataRAM2

0x7FCA000

0x3

DataRAM3

0x7FC0000

DataRAM2

0x7FC8000

DataRAM1

0x7FCE000

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