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DA14682 Datasheet(PDF) 3 Page - Dialog Semiconductor

Part # DA14682
Description  Bluetooth Low Energy 5.0 SoC with Enhanced Security and FLASH
PDF  459 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

DA14682 Datasheet(HTML) 3 Page - Dialog Semiconductor

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Datasheet
Revision 3.3
6-Feb-2020
CFR0011-120-00-FM Rev 5
3 of 459
© 2018-2020 Dialog Semiconductor
DA14682
Bluetooth Low Energy 5.0 SoC with Enhanced Security and FLASH
FINAL
13.4 DMA ARBITRATION . . . . . . . . . . . . . . . . . . . 80
13.5 FREEZING DMA CHANNELS. . . . . . . . . . . . 80
14 AES/Hash Engine . . . . . . . . . . . . . . . . . . . . . . . . . 81
14.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 81
14.1.1 AES/HASH engine. . . . . . . . . . . . . . . . 81
14.1.2 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
14.1.3 Modes . . . . . . . . . . . . . . . . . . . . . . . . . 82
14.1.4 HASH. . . . . . . . . . . . . . . . . . . . . . . . . . 82
14.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 83
15 ECC Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
15.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 86
15.1.1 Supported curves. . . . . . . . . . . . . . . . . 87
15.1.2 Supported high level algorithms . . . . . 87
15.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 87
15.2.1 Example: ECDSA signature generation 87
16 True Random Number Generator (TRNG). . . . . . 90
16.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 90
16.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 90
16.2.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . 90
17 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . 91
17.1 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 91
18 Wakeup Controller . . . . . . . . . . . . . . . . . . . . . . . . 92
18.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 92
18.2 PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 92
19 General purpose ADC . . . . . . . . . . . . . . . . . . . . . . 94
19.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 94
19.2 INPUT CHANNELS AND INPUT SCALE . . . 96
19.3 STARTING THE ADC . . . . . . . . . . . . . . . . . . 96
19.4 ADC CONVERSION MODES . . . . . . . . . . . . 96
19.4.1 Manual Mode . . . . . . . . . . . . . . . . . . . . 96
19.4.2 Continuous Mode. . . . . . . . . . . . . . . . . 96
19.5 NON-IDEAL EFFECTS . . . . . . . . . . . . . . . . . 96
19.6 SAMPLING TIME (SMPL_TIME). . . . . . . . . . 97
19.7 OVERSAMPLING . . . . . . . . . . . . . . . . . . . . . 97
19.8 CHOPPING . . . . . . . . . . . . . . . . . . . . . . . . . . 98
19.9 OFFSET CALIBRATION . . . . . . . . . . . . . . . . 98
19.10 ZERO-SCALE ADJUSTMENT . . . . . . . . . . 98
19.11 COMMON MODE ADJUSTMENT . . . . . . . . 98
19.12 INPUT IMPEDANCE, INDUCTANCE, AND IN-
PUT SETTLING. . . . . . . . . . . . . . . . . . . . . . . . 99
20 Sample Rate Converter (SRC) . . . . . . . . . . . . . . 100
20.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 100
20.1.1 I/O channels. . . . . . . . . . . . . . . . . . . . 100
20.1.2 I/O multiplexers . . . . . . . . . . . . . . . . . 100
20.1.3 Input and Output Sample rate conversion
100
20.1.4 SRC conversion modes of operation . 100
20.1.5 DMA operation . . . . . . . . . . . . . . . . . . 101
20.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . 101
20.1.7 SRC use cases . . . . . . . . . . . . . . . . . 101
21 PDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
22 PCM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103
22.1 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 103
22.1.1 Interface Signals . . . . . . . . . . . . . . . . 103
22.1.2 Channel ACCESS . . . . . . . . . . . . . . . 103
22.1.3 Channel delay . . . . . . . . . . . . . . . . . . 104
22.1.4 Clock generation . . . . . . . . . . . . . . . . 104
22.1.5 DATA FORMATS . . . . . . . . . . . . . . . . 105
22.1.6 IOM mode . . . . . . . . . . . . . . . . . . . . . 106
22.1.7 External synchronisation . . . . . . . . . . 106
23 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
23.1 UART (RS232) SERIAL PROTOCOL . . . . . 108
23.2 IRDA 1.0 SIR PROTOCOL . . . . . . . . . . . . . 109
23.3 CLOCK SUPPORT . . . . . . . . . . . . . . . . . . . .110
23.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . .111
23.5 PROGRAMMABLE THRE INTERRUPT . . . .111
23.6 SHADOW REGISTERS . . . . . . . . . . . . . . . .113
23.7 DIRECT TEST MODE . . . . . . . . . . . . . . . . . .113
24 SPI+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
24.1 OPERATION WITHOUT FIFOS . . . . . . . . . .114
24.2 9 BITS MODE . . . . . . . . . . . . . . . . . . . . . . . .115
24.3 TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
25 I2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
25.1 I2C BUS TERMS . . . . . . . . . . . . . . . . . . . . . .119
25.1.1 Bus Transfer Terms . . . . . . . . . . . . . . 120
25.2 I2C BEHAVIOUR. . . . . . . . . . . . . . . . . . . . . 120
25.2.1 START and STOP Generation . . . . . . 121
25.2.2 Combined Formats . . . . . . . . . . . . . . 121
25.3 I2C PROTOCOLS . . . . . . . . . . . . . . . . . . . . 121
25.3.1 START and STOP Conditions . . . . . . 121
25.3.2 Addressing Slave Protocol. . . . . . . . . 121
25.3.3 Transmitting and Receiving Protocol . 122
25.4 MULTIPLE MASTER ARBITRATION . . . . . 124
25.5 CLOCK SYNCHRONIZATION . . . . . . . . . . 125
25.6 OPERATION MODES . . . . . . . . . . . . . . . . . 125
25.6.1 Slave Mode Operation . . . . . . . . . . . . 126
25.7 MASTER MODE OPERATION . . . . . . . . . . 128



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