DS2792 Programmable Fuel Gauge with UART Interface

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SYSTEM RESET

Several reset sources are provided for microcontroller control. Although code execution is halted in the reset state,

OSCI continues to run.

Power-On Reset: An internal power-on reset circuit enhances system reliability. This circuit forces the device to

occur:

Watchdog Timer Reset: Software can determine if a reset is caused by a watchdog timeout by checking the

watchdog timer reset flag (WTRF) in the WDCN register. Execution resumes at location 8000h following a

watchdog timer reset.

External System Reset: Asserting the external

RST (port P0.2) pin low causes the device to enter the reset state.

The external reset function is described in the MAXQ Family User's Guide. Execution resumes at location 8000h

after the

RST pin is released.

MAXQ20 CORE POWER MANAGEMENT

The DS2792 is designed for low-power battery-monitoring applications. The peripherals have been designed with

the ability to wake the processor from SLEEP or ANALOG mode any time software intervention is needed. Power

management is optimized in the applications by performing any necessary processing as quickly as possible, and

re-entering the low power SLEEP or ANALOG mode. Processing resumes from SLEEP or ANALOG mode via any

of the following sources (when enabled):

RST pin.

Note: No division of the internal system clock is supported, subsequently the PMME and CD[1:0] bits described in

the MAXQ Family User’s Guide are not implemented in the DS2792.

WATCHDOG TIMER

The watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. The

watchdog timer is a hardware timer designed to be periodically reset by the application software. If the software

operates correctly, the timer is reset before it reaches its maximum count. However, if undesireable code execution

prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor.

The watchdog timer in the DS2792 differs in two respects from the one described in the MAXQ Family User's

Guide: 1) the clock used by the timer is the 70kHz OSCA clock that runs independently of the 1MHz OSCI (or

system) clock, and 2) the watchdog interrupt is an asynchronous interrupt that can bring the processor out of stop

mode.

The watchdog timer is controlled through bits in the WDCN register. Its timeout period can be set to one of the four

programmable intervals ranging from 2

occurs at the end of this timeout period, which is 512 OSCA clock periods, or 7.3ms, before the reset.