DS1877 datasheet(21/65 Pages) MAXIM

21 / 65 page

Maxim Integrated

SFP Controller for Dual Rx Interface

DS1877

of SCL plus the setup and hold time requirements

(Figure 12). Data is shifted into the device during the

rising edge of the SCL.

Bit Read: At the end of a write operation, the master

must release the SDA bus line for the proper amount

of setup time (Figure 12) before the next rising edge

of SCL during a bit read. The device shifts out each

bit of data on SDA at the falling edge of the previous

SCL pulse and the data bit is valid at the rising edge

of the current SCL pulse. Remember that the master

generates all SCL clock pulses, including when it is

reading bits from the slave.

Acknowledgement (ACK and NACK): An acknowl-

edgement (ACK) or not-acknowledge (NACK) is

always the 9th bit transmitted during a byte transfer.

The device receiving data (the master during a read

or the slave during a write operation) performs an ACK

by transmitting a zero during the 9th bit. A device per-

forms a NACK by transmitting a one during the 9th bit.

Timing (Figure 12) for the ACK and NACK is identical

to all other bit writes. An ACK is the acknowledgment

that the device is properly receiving data. A NACK is

used to terminate a read sequence or as an indication

that the device is not receiving data.

Byte Write: A byte write consists of 8 bits of informa-

tion transferred from the master to the slave (most

significant bit first) plus a 1-bit acknowledgement

from the slave to the master. The 8 bits transmitted by

the master are done according to the bit write defini-

tion and the acknowledgement is read using the bit

read definition.

Byte Read: A byte read is an 8-bit information transfer

from the slave to the master plus a 1-bit ACK or NACK

from the master to the slave. The 8 bits of information

that are transferred (most significant bit first) from the

slave to the master are read by the master using the

bit read definition, and the master transmits an ACK

using the bit write definition to receive additional data

bytes. The master must NACK the last byte read to

terminate communication so the slave returns control

of SDA to the master.

Slave Address Byte: Each slave on the I2C bus

responds to a slave address byte sent immediately

following a START condition. The slave address byte

contains the slave address in the most significant 7

bits and the R/W bit in the least significant bit.

The device responds to three slave addresses.

The auxiliary memory always responds to a fixed

I2C slave address, A0h. (If the main device’s slave

address is programmed to be A0h/B0h, access to

the auxiliary memory is disabled.) The Lower Memory

and Tables 00h–05h respond to I2C slave addresses

whose lower 3 bits are configurable (A0h−AEh,

B0h−BEh) using the DEVICE ADDRESS byte (Table

02h, Register 8Bh). The user also must set the ASEL

bit (Table 02h, Register 88h) for this address to be

active. By writing the correct slave address with R/W

= 0, the master indicates it writes data to the slave.

If R/W = 1, the master reads data from the slave.

If an incorrect slave address is written, the device

assumes the master is communicating with another

I2C device and ignores the communications until the

next START condition is sent.

Memory Address: During an I2C write operation

to the device, the master must transmit a memory

address to identify the memory location where the

slave is to store the data. The memory address is

always the second byte transmitted during a write

operation following the slave address byte.

I2C Protocol

See Figure 13 for an example of I2C timing.

Writing a Single Byte to a Slave: The master must

generate a START condition, write the slave address

byte (R/W = 0), write the memory address, write

the byte of data, and generate a STOP condition.

Remember that the master must read the slave’s

acknowledgement during all byte write operations.

Writing Multiple Bytes to a Slave: To write multiple

bytes to a slave, the master generates a START

condition, writes the slave address byte (R/W = 0),

writes the memory address, writes up to 8 data

bytes, and generates a STOP condition. The device

writes 1 to 8 bytes (one page or row) with a single

write transaction. This is internally controlled by an

address counter that allows data to be written to con-

secutive addresses without transmitting a memory

address before each data byte is sent. The address

counter limits the write to one 8-byte page (one row

of the memory map). Attempts to write to additional

pages of memory without sending a STOP condition

between pages result in the address counter wrap-

ping around to the beginning of the present row.

For example: A 3-byte write starts at address 06h and

writes three data bytes (11h, 22h, and 33h) to three

“consecutive” addresses. The result is that addresses

06h and 07h would contain 11h and 22h, respec-

tively, and the third data byte, 33h, would be written

to address 00h.

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